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1. general description the isp1763a is a single-chip hi-speed universal serial bus (usb) on-the-go (otg) controller integrated with the advanced slave host controller and the isp1582 peripheral controller. the hi-speed usb host controller and peripheral controller comply with universal serial bus specification rev. 2.0 and support data transfer speeds of up to 480 mbit/s. the enhanced host controller interface (ehci) core implemented in the host controller is adapted from enhanced host controller interface specification for universal serial bus rev. 1.0 . the otg controller is compliant with on-the-go supplement to the usb specification rev. 1.3 . the isp1763a has two usb ports. port 1 can be configured to function as a downstream port, an upstream port, or as an otg port; port 2 is always configured as a downstream port. port 2 supports session request protocol (srp) detection from the b-device. the otg port supports host negotiation protocol (hnp) and srp as specified in on-the-go supplement to the usb specification rev. 1.3 . the isp1763a support multiple bus interfaces with 8-bit or 16-bit bus. the isp1763a can interface to processors with digital i/o voltages of 1.8 v or 3.3 v. 2. features ? compliant with: ? universal serial bus specification rev. 2.0 ? on-the-go supplement to the usb specification rev. 1.3 ? small form-factor for portable applications; available in vfqfpn64 and tfbga64 restriction of hazardous substances (rohs) compliant, halogen-free and lead-free packages ? low power consumption for portable applications ? host supports data transfer at high-speed (480 mbit/s), full-speed (12 mbit/s), and low-speed (1.5 mbit/s); supports disabling of high-speed mode on each port ? peripheral supports data transfer at high-speed (480 mbit/s) and full-speed (12 mbit/s) ? integrated transaction translator (tt) for original usb (full-speed and low-speed) support ? two usb ports: ? port 1: otg, host, or peripheral port ? port 2: host port only (supports srp detection) ? supports otg hnp and srp ? supports 8-bit or 16-bit cpu bus interface ? flexibility to interface with various types of processors: isp1763a hi-speed usb otg controller rev. 04 ? october 14, 2013 product data sheet
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 2 of 135 isp1763a hi-speed usb otg controller ? nor flash interface (multiplexed mode) ? nand flash interface (multiplexed mode) ? general multiplex interface ? sram interface ? single configurable interrupt (int) line for the host controller, peripheral controller, and otg controller ? integrated phase-locked loop (pll) supports external 12 mhz, 19.2 mhz, and 24 mhz crystal, and direct clock source ? supports remote wake-up from deep sleep mode ? supports interfacing i/o voltage of 1.8 v or 3.3 v; separate i/o voltage supply pins minimize crosstalk ? internal voltage regulator supplies 1.2 v to the digital core ? 3.0 v to 3.6 v supply voltage input range for the internal usb transceiver ? supports hybrid power mode; v cc(3v3) is not present, v cc(i/o) is powered ? host controller-specific features: ? ehci core is adapted from enhanced host controller interface specification for universal serial bus rev. 1.0 ? integrated tt for original usb device support on both the ports ? integrated 24 kb high-speed memory ? power switching and overcurrent reporting on per-port basis ? peripheral controller-specific features: ? compliant with universal serial bus specification rev. 2.0 ? integrated 4 kb memory to support seven in endpoints, seven out endpoints, and one fixed control in/out endpoint ? v bus detection in deep sleep mode ? otg controller-specific features: ? supports otg hnp and srp using status and control registers for the software implementation in otg dual-role devices ? integrated v bus voltage comparators ? integrated cable (id) detector ? programmable timers with high resolution (0.01 ms to 80 ms) 3. applications the isp1763a can be used to implement a dual-role usb device in any application, usb host or usb peripheral, depending on the cable connection. if the dual-role device is connected to a usb peripheral, it behaves like a usb host. the dual-role device can also be connected to a pc or any other usb host, and behave like a usb peripheral. 3.1 host or peripheral roles ? tv/tv box: ? play, upload, or download media files from or to usb memory disk ? dvd player: ? play, upload, or download media files from or to usb memory disk ? mobile phone to or from:
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 3 of 135 isp1763a hi-speed usb otg controller ? mobile phone: exchange contact information ? digital still camera: e-mail pictures or upload pictures to the web ? mp3 player: upload or download/broadcast music ? mass storage: upload or download files ? scanner: scan business cards ? printer ? netbook ? set-top box 4. ordering information 5. marking [1] the package marking is the first line of text on the ic package and can be used for ic identification. table 1. ordering information commercial product code package description packing minimum sellable quantity ISP1763AETTM tfbga64; 64 balls; body 4 4 0.8 mm 13 inch tape and reel non-dry pack 4000 pieces isp1763ahnum vfqfpn64; 64 terminals; body 9 9 1.0 mm 13 inch tape and reel dry pack 1000 pieces table 2. marking codes type number marking code [1] ISP1763AETTM 1763a isp1763ahnum 1763a
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 4 of 135 isp1763a hi-speed usb otg controller 6. block diagram the figure shows the vfqfpn pinout. for the tfbga ballout, see table 3 . (1) only applicable to the tfbga package. (2) only applicable to the vfqfpn package. fig 1. block diagram isp1763a interface control logic 004aaa986 host controller ram 24 kb peripheral controler ram 4 kb memory arbiter host controller peripheral controler dynamic port routing and otg controller atx1 regulator atx2 pll por ad[15:0] a[7:0] ale/adv_n cle cs_n/ce_n rd_n/ds_n/ re_n/oe_n w r_n/rw_n/ we_n int dreq dack dgnd (1) oc1/v bus1 rref1 dp1 dm1 id psw1_n oc2/v bus2 dp2 dm2 psw2_n v cc(3v3) v reg(1v2) gnd (2) (die pad) agnd reset_n x1/clkin x2 freqsel 1 freqsel 2 v cc(i/o) 4 8 3 rref2 isp1763a 1, 43, 47, 51, 53, 59 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19 6, 15, 25, 35 20, 32, 46 21 22 23 24 26, 27, 28, 29, 30, 31, 33, 34 36 37 38 39 40 41 42 44 45 48 49 50 52 agnd agnd 55 54 56 57 58 60 61 62 63 64
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 5 of 135 isp1763a hi-speed usb otg controller 7. pinning information 7.1 pinning fig 2. pin configuration tfbga64 004aab15 3 isp1763a transparent top view b all a1 i ndex area 18 7 6 5 4 3 2 b c d e f g h a
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 6 of 135 isp1763a hi-speed usb otg controller 7.2 pin description fig 3. pin configuration vfqfpn64 004aab154 isp1763a transparent top view agnd ad0 ad1 ad2 ad3 v cc(i/o) ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 v cc(i/o) ad12 psw1_n agnd v reg(1v2) x2 x1/clkin agnd freqsel 2 freqsel 1 reset_n cle ale/adv_ n dack dreq v cc(i/o) a7 a6 ad13 ad14 ad15 v reg(1v2) cs_n/ce_n r d_n/ds_n/re_n/oe_n wr_n/rw_n/we_n int v cc(i/o) a0 a1 a2 a3 a4 a5 v reg(1v2) dp2 agnd dm2 oc2/v bus 2 psw2_n agnd rref2 v cc(3v3) id agnd dp1 agnd dm1 agnd rref1 oc1/v bus 1 b all a1 i ndex area 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 table 3. pin description symbol [1] pin type [2] description tfbga64 vfqfpn64 agnd b2 1 p analog ground ad0 b1 2 i/o bit 0 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad1 c2 3 i/o bit 1 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad2 c1 4 i/o bit 2 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 7 of 135 isp1763a hi-speed usb otg controller ad3 c3 5 i/o bit 3 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant v cc(i/o) d2 6 p i/o supply voltage; connect a 0.1 f decoupling capacitor ad4 d1 7 i/o bit 4 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad5 c4 8 i/o bit 5 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad6 e1 9 i/o bit 6 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad7 e2 10 i/o bit 7 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad8 f1 11 i/o bit 8 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad9 d3 12 i/o bit 9 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad10 d4 13 i/o bit 10 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad11 g1 14 i/o bit 11 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant v cc(i/o) f2 15 p i/o supply voltage; connect a 0.1 f decoupling capacitor ad12 e3 16 i/o bit 12 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad13 h1 17 i/o bit 13 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad14 g2 18 i/o bit 14 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant ad15 h2 19 i/o bit 15 of the address and data bus bidirectional pad; push-pull input; three-state output; 3.3 v tolerant v reg(1v2) h3 20 p core power 1.2 v; connect a 4.7 f decoupling capacitor either on this pin or on pin 46 (ball c7) table 3. pin description ?continued symbol [1] pin type [2] description tfbga64 vfqfpn64
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 8 of 135 isp1763a hi-speed usb otg controller cs_n/ce_n g3 21 i chip select input; 3.3 v tolerant rd_n/ds_n/ re_n/oe_n f3 22 i read enable, write, or read latch; when not in use, connect to v cc(i/o) input; 3.3 v tolerant wr_n/rw_n/ we_n h4 23 i write enable; when not in use, connect to v cc(i/o) input; 3.3 v tolerant int g4 24 o interrupt output remark: when the isp1763a is in power-down mode, the int pin is a high-impedance i/o. external pull-down resistors are recommended to minimize the i/o leakage. push-pull output; 3.3 v tolerant v cc(i/o) f4 25 p i/o supply voltage; connect a 0.1 f decoupling capacitor a0 h5 26 i bit 0 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant a1 g5 27 i bit 1 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant a2 h6 28 i bit 2 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant a3 e4 29 i bit 3 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant a4 h7 30 i bit 4 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant a5 g6 31 i bit 5 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant v reg(1v2) h8 32 p core power 1.2 v input; for normal operation, this pin must be connected to pin 20 or pin 46 for the vfqfpn64 package and ball h3 or ball c7 for the tfbga64 package a6 f5 33 i bit 6 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant a7 g7 34 i bit 7 of the address bus; when not in use, connect to gnd input; 3.3 v tolerant v cc(i/o) f6 35 p i/o supply voltage; connect a 0.1 f decoupling capacitor dreq g8 36 o dma request; when not in use, pull-down to gnd through a 10 k resistor remark: when the isp1763a is in power-down mode, the dreq pin is a high-impedance i/o. external pull-down resistors are recommended to minimize the i/o leakage. push-pull output; 3.3 v tolerant dack f7 37 i dma acknowledge; when not in use, connect to gnd through a 10 k resistor input; 3.3 v tolerant table 3. pin description ?continued symbol [1] pin type [2] description tfbga64 vfqfpn64
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 9 of 135 isp1763a hi-speed usb otg controller ale/adv_n f8 38 i address latch enable input; 3.3 v tolerant cle e6 39 i command latch enable input; 3.3 v tolerant reset_n e7 40 i internal regulator power-down control; when not in use, connect to v cc(i/o) input; 3.3 v tolerant freqsel1 e8 41 i input clock frequency selection pin 1 input; 3.3 v tolerant freqsel2 d8 42 i input clock frequency selection pin 2 input; 3.3 v tolerant agnd d7 43 p analog ground x1/clkin c8 44 ai crystal oscillator or clock input; 1.2 v peak input allowed x2 b8 45 ao crystal oscillator output; leave open if an external clock is applied on pin x1/clkin v reg(1v2) c7 46 p core power 1.2 v; connect a 4.7 f decoupling capacitor either on this pin or on pin 20 (ball h3) agnd - 47 p analog ground dgnd e5 - p digital ground psw1_n d6 48 od port 1 power switch; when not in use, connect to v cc(3v3) through a 10 k resistor open-drain output; 5 v tolerant oc1/v bus1 a8 49 ai/o ? overcurrent input (oc1) for the host functionality; an external power switch is used ? v bus1 for the otg and peripheral functionality; connected to v bus detectors, and v bus srp charge and discharge circuit. when not in use, connect to v cc(3v3) through a 10 k resistor. 5 v tolerant rref1 a7 50 ai port 1 reference resistor connection; see section 8.12.4 agnd b7 51 p analog ground dm1 a6 52 ai/o port 1 dm; connect to the d ? pin of the usb connector agnd b6 53 p analog ground dp1 a5 54 ai/o port 1 dp; connect to the d+ pin of the usb connector agnd c6 55 p port 1 analog gnd id b5 56 ai port 1 id pin (an internal pull-up resistor is present on this pin) v cc(3v3) a4 57 p supply voltage rref2 a3 58 ai port 2 reference resistor connection; see section 8.12.4 agnd c5 59 p analog ground psw2_n b4 60 od port 2 power switch; when not in use, connect to v cc(3v3) through a 10 k resistor open-drain output; 5 v tolerant table 3. pin description ?continued symbol [1] pin type [2] description tfbga64 vfqfpn64
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 10 of 135 isp1763a hi-speed usb otg controller [1] symbol names ending with underscore n (for example, name_n) represent active-low signals. [2] i = input only; o = output only; i/o = digital input/output; od = open-drain output; ai = analog input; ao = analog output; ai/o = analog input/output; p = power or ground. oc2/v bus2 d5 61 ai port 2 overcurrent input or v bus detection; when not in use, connect to v cc(3v3) through a 10 k resistor 5 v tolerant dm2 a2 62 ai/o port 2 dm; connect to the d ? pin of the usb connector agnd b3 63 p port 2 analog ground dp2 a1 64 ai/o port 2 dp; connect to the d+ pin of the usb connector gnd - die pad p ground supply; down bonded to the exposed die pad (heat sink); to be connected to the pcb ground table 3. pin description ?continued symbol [1] pin type [2] description tfbga64 vfqfpn64
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 11 of 135 isp1763a hi-speed usb otg controller 8. functional description 8.1 cpu bus interface the isp1763a has a fast advance general-purpose interface to communicate with most types of microcontrollers and microprocessors. this microcontroller interface is configured using pins ale/adv_n and cle to accommodate most types of interfaces. the bus interface supports 8-bit and 16-bit, which can be configured using bit data_bus_width. four bus interface types are selected using inputs ale/adv_n and cle during power-up, the rd_n/ds_n/re_n/oe_n and cs_n/ce_n pins, or the reset_n pin. ta b l e 4 provides details of bus configurations for each mode. table 4. bus configuration modes bus mode ale/adv_n cle data_bus_width signal description sram 8-bit high high 1 ? a[7:0]: 8-bit address bus ? ad[7:0]: 8-bit data bus ? write (wr_n), read (rd_n), chip select (cs_n): control signals for normal sram mode ? write (wr_n/rw_n), data strobe (ds_n), chip select (cs_n): control signals for proprietary sram mode (see figure 14 ) ? dack: dma acknowledge input ? dreq: dma request output sram 16-bit high high 0 ? a[7:0]: 8-bit address bus ? ad[15:0]: 16-bit data bus ? write (wr_n), read (rd_n), chip select (cs_n): control signals ? write (wr_n/rw_n), data strobe (ds_n), chip select (cs_n): control signals for proprietary sram mode (see figure 14 ) ? dack: dma acknowledge input ? dreq: dma request output nand 8-bit low low 1 ? ad[7:0]: 8-bit data bus ? ale, cle, write enable, read enable (re_n), chip enable: control signals nand 16-bit low low 0 ? ad[15:0]: 16-bit data bus ? ale, cle, write enable, read enable, chip enable: control signals nor 8-bit high low 1 ? ad[7:0]: 8-bit data bus ? adv_n, write enable, output enable, chip select: control signals
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 12 of 135 isp1763a hi-speed usb otg controller 8.2 interface mode lock the bus interface can be locked in any of the modes, sram, nand, nor, or general multiplex, using bit 3 of the hw mode control register. to lock the interface in a particular mode: 1. read bits 7 and 6 of the sw reset register. 2. set bit 3 of the hw mode control register to logic 1. 3. read bits 7 and 6 of the sw reset register to ensure that the interface is locked in the desired mode. 8.3 sram bus interface mode the bus interface will be in sram 16-bit mode if pins ale/adv_n and cle are high, when: ? the cs_n/ce_n pin goes low, and the rd_n/ds_n/re_n/oe_n pin goes low, or ? the reset_n pin goes from low to high. then, if the data_bus_width bit is set, the bus interface will be in sram 8-bit mode. nor 16-bit high low 0 ? ad[15:0]: 16-bit data bus ? adv_n, write enable, output enable, chip select: control signals general multiplex 8-bit low high 1 ? ad[7:0]: 8-bit data bus ? ale, write (wr_n), read (rd_n), chip select: control signals general multiplex 16-bit low high 0 ? ad[15:0]: 16-bit data bus ? ale, write (wr_n), read (rd_n), chip select: control signals table 4. bus configuration modes ?continued bus mode ale/adv_n cle data_bus_width signal description table 5. pinning information of the bus interface sram mode nand mode nor mode general multiplex mode type description ad[15:0] ad[15:0] ad[15:0] ad[15:0] i/o data or address bus a[7:0] - - - i address bus - ale adv_n ale i address or command valid - cle - - i address or command valid cs_n ce_n cs_n cs_n i chip select read/data strobe re_n oe_n read/data strobe i read control write/read or write we_n we_n write/read or write i write control int int int int o interrupt request dreq - - dreq o dma request dack - - dack i dma acknowledge
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 13 of 135 isp1763a hi-speed usb otg controller in sram mode, a[7:0] is the 8-bit address bus and ad[15:0] is the separate 16-bit data bus. the isp1763a pins rd_n/ds_n/re_n/oe_n and wr_n/rw_n/we_n are the read and write strobes. the sram bus interface supports both 8-bit and 16-bit bus width that can be configured by setting or clearing bit data_bus_width. the dma transfer is also applicable to this interface. 8.4 nand bus interface mode the bus interface will be in nand 16-bit mode if pins ale/adv_n and cle are low, when: ? the cs_n/ce_n pin goes low, and the rd_n/ds_n/re_n/oe_n pin goes low, or ? the reset_n pin goes from low to high. then, if the data_bus_width bit is set, the bus interface will be in nand 8-bit mode. the nand bus interface supports most advance application processors. the command-address-data multiplexed bus is an 8-bit or 16-bit connection. the nand flash interface access consists of three phases: command, address, and data. the command phase is ignored. the address in the nand flash interface is sequentially sent in address cycles. for the isp1763a application, an 8-bit address is sufficient to address all on-chip registers and buffers; see figure 4 . the last byte address latched will be the accessed address if there are several address cycles. the data length can vary from one byte to multiple bytes. for example, to access the data port of the peripheral controller, the maximum data length can reach 1024 bytes. 8.5 nor bus interface mode the bus interface will be in nor 16-bit mode, if pin ale/adv_n is high and pin cle is low, when: ? the cs_n/ce_n pin goes low, and the rd_n/ds_n/re_n/oe_n pin goes low, or fig 4. write operation 004aaa625 cle cs_n/ce_n w r_n/rw_n/ we_n ale/adv_n ad[15:0] cmd addr data data data rd_n/ds_n/ re_n/oe_n
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 14 of 135 isp1763a hi-speed usb otg controller ? the reset_n pin goes from low to high. then if the data_bus_width bit is set, the bus interface will be in nor 8-bit mode. the nor flash interface access consists of two phases: address and data. the address is valid when cs_n/ce_n and adv_n are low, and the address is latched at the rising edge of adv_n. for a read operation, we_n must be high. oe_n is the data output control. when active, the addressed register or the buffer data is driven to the i/o bus. the read operation is completed when cs_n/ce_n is deasserted. for a write operation, oe_n must be high. the we_n assertion can start when adv_n is deasserted. we_n is the data input strobe signal. when deasserted, data will be written to the addressed register or the buffer. the write operation is completed when cs_n/ce_n is deasserted. 8.6 general multiplex bus interface mode the bus interface will be in general multiplex 16-bit mode, if pin ale/adv_n is low and pin cle is high, when: ? the cs_n/ce_n pin goes low, and the rd_n/ds_n/re_n/oe_n pin goes low, or ? the reset_n pin goes from low to high. then if the data_bus_width bit is set, the bus interface will be in general multiplex 8-bit mode.the general multiplex bus interface supports most advance application processors. the general multiplex interface access consists of two phases: address and data. the address is valid when ale/adv_n goes high, and the address is latched at the falling edge of ale/adv_n. for a read operation, wr_n/rw_n/we_n must be high. rd_n/ds_n/re_n/oe_n is the data output control. when active, the addressed register or the buffer data is driven to the i/o bus. the read operation is completed when cs_n/ce_n is deasserted. for a write operation, rd_n/ds_n/re_n/oe_n must be high. the wr_n/rw_n/we_n assertion can start when ale/adv_n is deasserted. wr_n/rw_n/we_n is the data input strobe signal. when deasserted, data will be written to the addressed register or the buffer. the write operation is completed when cs_n/ce_n is deasserted. the dma transfer is also applicable to this interface. 8.7 dma controller the dma controller of the isp1763a is used to transfer data between the system memory and local buffers. it shares data bus ad[15:0] and control signals wr_n/rw_n/we_n, rd_n/ds_n/re_n/oe_n, and cs_n/ce_n. the logic is dependent on the bus interface mode setting. dreq is from the isp1763a to indicate the start of dma. dack is used to differentiate if data transferred is for the dma or pio access. when dack is asserted, it indicates that it is still in dma mode. when dack is deasserted, it indicates that pio is to be accessed. ale/adv_n and cle (address phase) are ignored in a dma access cycle. correct data will be captured only on the data phase (the rising edge of wr_n/rw_n/we_n and rd_n/ds_n/re_n/oe_n). the dma controller of the isp1763a has only one dma channel. therefore, only one dma transfer may take place at a time.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 15 of 135 isp1763a hi-speed usb otg controller the isp1763a supports only counter mode. dynamically assign the dma transfer counter for each dma transfer. the transfer ends once the transfer counter reaches zero. if the transfer counter is larger than the burst counter, the dreq signal will deassert at the end of each burst transfer. dreq will re-assert at the beginning of each burst. for a 16-bit dma transfer, the minimum burst length is 2 bytes. this means that the burst length is only one dma cycle. therefore, dreq and dack will assert and deassert at each dma cycle. in peripheral dma, the bits in the interrupt reason register will be asserted to indicate that the dma transfer has either successfully completed or terminated. setting the control bits in the dma command register will start, stop, or reset the dma transfer. table 6. register address device register cpu address host register cpu address otg register cpu address address 00h usbcmd 8ch otg control (set) e4h mode 0ch usbsts 90h otg control (clear) e6h interrupt configuration 10h frindex 98h otg status (rd only) e8h debug 12h configflag 9ch otg interrupt latch (set) ech dcinterruptenable 14h portsc1 a0h otg interrupt latch (clear) eeh endpoint index 2ch iso ptd done map a4h otg interrupt enable fall (set) f0h control function 28h iso ptd skip map a6h otg interrupt enable fall (clear) f2h data port 20h iso ptd last ptd a8h otg interrupt enable rise (set) f4h buffer length 1ch int ptd done map aah otg interrupt enable rise (clear) f6h dcbufferstatus 1eh int ptd skip map ach otg timer (lower word: set) f8h epmaxpacketsize 04h int ptd last ptd aeh otg timer (lower word: clear) fah endpoint type 08h atl ptd done map b0h otg timer (higher word: set) fch dma command 30h atl ptd skip map b2h otg timer (higher word: clear) feh dma transfer counter 34h atl ptd last ptd b4h dcdmaconfiguration 38h hw mode control b6h dma hardware 3ch sw reset b8h dma interrupt reason 50h hcbufferstatus bah dma interrupt enable 54h hcdmaconfiguration bch dma endpoint 58h atl done timeout c0h dma burst counter 64h memory c4h dcinterrupt 18h data c6h chip id 70h edge interrupt count c8h frame number 74h dma start address cch scratch 78h dma data port 60h unlock device 7ch power down control d0h interrupt pulse width 80h hcinterrupt d4h test mode 84h hcinterruptenable d6h iso irq mask or d8h int irq mask or dah atl irq mask or dch
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 16 of 135 isp1763a hi-speed usb otg controller 8.8 on-the-go (otg) controller 8.8.1 introduction otg is a supplement to the hi-speed usb specification that augments existing usb peripherals by adding to these peripherals limited host capability to support other targeted usb peripherals. it is primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. non-portable devices, even standard hosts, can also benefit from otg features. the isp1763a otg controller is designed to perform all the tasks specified in the otg supplement. it supports hnp and srp for dual-role devices. the isp1763a uses the software implementation of hnp and srp for maximum flexibility. a set of otg registers provides the control and status monitoring capabilities to support software hnp or srp. usb transceivers, timers, and analog components required by otg are also integrated on-chip. the analog components include: ? voltage comparators ? pull-up or pull-down resistors on data lines ? charging or discharging resistors for v bus 8.8.2 dual-role device when port 1 of the isp1763a is configured in otg mode, it can be used as an otg dual-role device. a dual-role device is a usb device that can function either as a host or as a peripheral. as a host, the isp1763a can support all four types of transfers, control, bulk, isochronous, and interrupt, at high-speed, full-speed, or low-speed. as a peripheral, the isp1763a can support two control endpoints, and up to seven in endpoints and seven out endpoints that can be programmed to any of the four transfer types. the default role of the isp1763a is controlled by the id pin, which in turn is controlled by the type of plug connected to the micro-ab receptacle. if id = low (micro-a plug connected), it becomes an a-device, which is a host by default. if id = high (micro-b plug connected), it becomes a b-device, which is a peripheral by default. both the a-device and the b-device work on a session basis. a session is defined as the period of time during which devices exchange data. a session starts when v bus is driven and ends when v bus is turned off. both the a-device and the b-device may start a session. during a session, the role of the host can be transferred back and forth between the a-device and the b-device any number of times by using hnp. if the a-device wants to start a session, it turns on v bus by enabling the external charge pump. the b-device detects that v bus has risen above the b_sess_vld level and assumes the role of a peripheral asserting its pull-up resistor on the dp line. the a-device detects the remote pull-up resistor and assumes the role of a host. then the a-device can iso irq mask and deh int irq mask and e0h atl irq mask and e2h table 6. register address ?continued device register cpu address host register cpu address otg register cpu address
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 17 of 135 isp1763a hi-speed usb otg controller communicate with the b-device as long as it wishes. when the a-device finishes communicating with the b-device, the a-device turns off v bus and both the devices finally go into the idle state. if the b-device wants to start a session, it must initiate srp by data line pulsing and v bus pulsing. when the a-device detects any of these srp events, it turns on its v bus . (note: only the a-device is allowed to drive v bus .) the b-device assumes the role of a peripheral, and the a-device assumes the role of a host. the a-device detects that the b-device can support hnp by getting the otg descriptor from the b-device. the a-device will then enable the hnp hand-off by using setfeature (b_hnp_enable) and then go into the suspend state. the b-device signals it is claiming the host role by deasserting its pull-up resistor. the a-device acknowledges by going into the peripheral state. the b-device then assumes the role of a host and communicates with the a-device as long as it wishes. when the b-device finishes communicating with the a-device, both the devices finally go into the idle state. 8.8.3 session request protocol (srp) as a dual-role device, the isp1763a can initiate and respond to srp. the b-device initiates srp by data line pulsing, followed by v bus pulsing. the a-device can detect data line pulsing. 8.8.3.1 b-device initiating srp the isp1763a can initiate srp by performing the following steps: 1. detect initial conditions (read id_gnd, b_sess_end, and se0_2ms of the otg interrupt source register). 2. start data line pulsing (set dp_pullup of the otg control register to logic 1). 3. wait for 5 ms to 10 ms. 4. stop data line pulsing (set dp_pullup of the otg control register to logic 0). 5. start v bus pulsing (set vbus_chrg of the otg control register to logic 1). 6. wait for 10 ms to 20 ms. 7. stop v bus pulsing (set vbus_chrg of the otg control register to logic 0). 8. discharge v bus for about 30 ms (by using vbus_dischrg of the otg control register), optional. the b-device must complete both data line pulsing and v bus pulsing within 100 ms. 8.8.3.2 a-device responding to srp the a-device must be able to respond to one of the two srp events: data line pulsing or v bus pulsing. 8.8.4 host negotiation protocol (hnp) hnp is used to transfer control of the host role between the default host (a-device) and the default peripheral (b-device) during a session. when the a-device is ready to give up its role as a host, it will condition the b-device using setfeature (b_hnp_enable) and will go into suspend. if the b-device wants to use the bus at that time, it signals a disconnect to the a-device. then, the a-device will take the role of peripheral and the b-device will take the role of a host.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 18 of 135 isp1763a hi-speed usb otg controller 8.8.4.1 sequence of hnp events the sequence of events for hnp as observed on the usb bus is illustrated in figure 5 . as can be seen in figure 5 : 1. the a-device completes using the bus and stops all bus activity (that is, suspends the bus). 2. the b-device detects that the bus is idle for more than 5 ms and begins hnp by turning off the pull-up on dp. this allows the bus to discharge to the se0 state. 3. the a-device detects se0 on the bus and recognizes this as a request from the b-device to become a host. the a-device responds by turning on its dp pull-up within 3 ms of first detecting se0 on the bus. 4. after waiting for 30 s to ensure that the dp line is not high because of the residual effect of the b-device pull-up, the b-device notices that the dp line is high and the dm line is low, that is, j state. this indicates that the a-device has recognized the hnp request from the b-device. at this point, the b-device becomes a host and asserts bus reset to start using the bus. the b-device must assert the bus reset, that is, se0, within 1 ms of the time that the a-device turns on its pull-up. 5. when the b-device completes using the bus, it stops all bus activities. optionally, the b-device may turn on its dp pull-up at this time. 6. the a-device detects lack of bus activity for more than 3 ms and turns off its dp pull-up. alternatively, if the a-device has no further need to communicate with the b-device, the a-device may turn off v bus and end the session. 7. the b-device turns on its pull-up. 8. after waiting 30 s to ensure that the dp line is not high because of the residual effect of the a-device pull-up, the a-device notices that the dp line is high (and the dm line is low) indicating that the b-device is signaling a connect and is ready to respond as a peripheral. at this point, the a-device becomes a host and asserts the bus reset to start using the bus. fig 5. hnp sequence of events a-device 1 5 7 2 3 4 6 8 b-device 004aaa07 9 d p composite legend dp driven pull-up dominates pull-down dominates normal bus activity
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 19 of 135 isp1763a hi-speed usb otg controller 8.8.5 power saving in the idle state and during wake-up the isp1763a can be put in power saving mode if the otg device is not in a session. this significantly reduces the power consumption. in this mode, both the peripheral controller and the host controller are suspended, the pll and the oscillator are stopped, and the external charge pump is in the suspend state. as an otg device, however, the isp1763a is required to respond to srp events. to support this, a lazyclock is kept running when the chip is in power-saving mode. an srp event will wake up the chip, that is, enable the pll and the oscillator. besides this, an id change or b_sess_vld detection can also wake up the chip. these wake-up events can be enabled or disabled by programming the related bits of the otg interrupt enable register before putting the chip in power saving mode. if the bit is set, then the corresponding event (status change) will wake up the isp1763a. if the bit is cleared, then the corresponding event will not wake up the isp1763a. you can also wake up the isp1763a from power-saving mode by using the software. this is accomplished by accessing any of the isp1763a registers. accessing a register will assert cs_n/ce_n and rd_n/ds_n/re_n/oe_n of the isp1763a, and therefore, set it awake. 8.9 usb host controller 8.9.1 isp1763a usb host controller and hub internal architecture the ehci block and the hi-speed usb hub block are the main components of the advanced slave host controller. the ehci is the latest generation design with improved data bandwidth. the ehci in the isp1763a is adapted from enhanced host controller interface specification for universal serial bus rev. 1.0 . the internal hi-speed usb hub block replaces the companion host controller block used in the original architecture of a pci hi-speed usb host controller to handle full-speed and low-speed modes. the host controller of the isp1763a architecture is a simplified hardware architecture that helps reduce cost and development time by eliminating the additional work involved in implementing the ohci software required to support full-speed and low-speed modes. figure 6 shows the internal architecture of the isp1763a host controller. the isp1763a host controller implements an ehci that has one internal port, the root hub port 1 (not available externally), on which the internal hub is connected. the two external ports are always routed to the internal hub. the internal hub is a hi-speed usb, including the tt. at power-on reset, followed by the host controller reset and initialization, the internal root hub port 1 will be polled until a new connection is detected showing the connection of the internal hub. the internal hi-speed usb hub is enumerated using a sequence similar to a standard hi-speed usb hub enumeration sequence, and the polling on the root hub is stopped because the internal hi-speed usb hub will never be disconnected.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 20 of 135 isp1763a hi-speed usb otg controller 8.9.2 host controller buffer memory block 8.9.2.1 general considerations the internal addressable host controller buffer memory is 24 kb. the total amount of memory allocated to the payload determines the maximum transfer size specified by a ptd, a larger internal memory size results in lesser cpu interruption for transfer programming. this means less time spent in context switching, resulting in better cpu usage. a larger buffer also implies a larger amount of data to be transferred. this transfer, however, can be done over a longer period of time, to maintain overall system performance. each transfer of the usb data on the usb bus can span up to a few milliseconds before requiring further cpu intervention for data movement. the internal architecture of the isp1763a host controller allows a flexible definition of the memory buffer for optimization of the data transfer on the cpu extension bus and the usb. it is possible to implement different data transfer schemes, depending on the number and type of usb devices present. for example, push-pull: data can be written to half of the memory while data in the other half is accessed by the host controller and sent on the usb bus. this is useful especially when a high-bandwidth continuous or periodic data flow is required. 8.9.2.2 structure of the host controller memory the internal memory is 24 kb: 4 kb ptd area and 20 kb payload area. fig 6. internal hub 004aaa51 4 ehci root hub internal hub (tt) port2 port1 enumeration and polling using actual tds
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 21 of 135 isp1763a hi-speed usb otg controller both the ptd and payload memory zones are divided into three dedicated areas for each main type of usb transfer: isochronous (iso), interrupt (int), and asynchronous transfer list (atl). as shown in table 7 , the ptd areas for iso, int, and atl are grouped at the beginning of the memory, occupying address range 0400h to 0fffh, following the registers address space. the payload or data area occupies the next memory address range 1000h to 5fffh, meaning that 20 kb of memory is allocated for the payload data. a maximum of 16 ptd areas and their allocated payload areas can be defined for each type of transfer. the structure of a ptd is similar for every transfer type and consists of eight double words (dws) that must be correctly programmed for correct usb data transfer. the reserved bits of a ptd must be set to logic 0. a detailed description of the ptd structure can be found in section 10.4 . the transfer size specified by the ptd determines the contiguous usb data transfer that can be performed without any cpu intervention. the respective payload memory area must be equal to the transfer size defined. the maximum transfer size is flexible and can be optimized, depending on the number and nature of usb devices or ptds defined and their respective maxpacketsize. the ram is structured in blocks of ptds and payloads so that while the usb is executing on an active transfer-based ptd, the processor can simultaneously fill up another block area in the ram. a ptd and its payload can then be updated on-the-fly without stopping or delaying any other usb transaction or corrupting the ram data. some of the design features are: ? the internal memory contains isochronous, interrupt, and asynchronous ptds, and defined payloads. ? internal memory address range calculation: memory address = (cpu address ? 0400h) (shift right >> 3). the base address is 0400h. both the cpu interface logic and the usb host controller require access to the internal isp1763a ram at the same time. the internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 mb/s. this bandwidth avoids any bottleneck on accesses both from the cpu interface and the internal usb host controller. table 7. memory address memory map cpu address memory address memory accessing iso ptd 0400h to 05ffh 0000h to 007fh ? configure the memory register ? bits 14 to 0: start address 1000h to 5fffh ? bit 15: reserved ? read/write data from or to the data register (address c6h of the isp1763a). ? the memory burst read and write is ended by any register access (other than c6h). int ptd 0800h to 09ffh 0080h to 00ffh atl ptd 0c00h to 0dffh 0100h to 017fh payload 1000h to 5fffh 0180h to 0b7fh
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 22 of 135 isp1763a hi-speed usb otg controller 8.9.3 interrupts the isp1763a will generate an int according to the source or event in the hcinterrupt register. the main steps to enable the int assertion are: 1. set global_intr_en (bit 0) in the hw mode control register. 2. define the int active as level or edge in intr_level (bit 1) of the hw mode control register. 3. define the int polarity as active low or high in intr_pol (bit 2) of the hw mode control register. these settings must match the int settings of the host processor. by default, interrupt is level-triggered and active low. 4. program the individual interrupt enable bits in the hcinterruptenable register. the software will need to clear the interrupt status bits in the hcinterrupt register before enabling individual interrupt enable bits. fig 7. memory segmentation and access block diagram 004aaa99 0 ptd1 ptd2 ptd16 ptd1 ptd2 . . . . ptd16 payload payload usb bus usb high-speed host and transaction translator (full-speed and low-speed) interrupt async payload ptd16 . . ptd1 ptd2 isochronous memory mapped input/output, memory management unit, slave dma controller and interrupt control registers arbiter control signals 240 mb/s address data (64 bits) ad[15:0] a[7:0] . . . . . . . . cs_n/ce_n rd_n/ds_n/ re_n/oe_n wr_n/rw_n/we_n int dreq dack cle ale/adv_n micro- processor
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 23 of 135 isp1763a hi-speed usb otg controller additional int characteristics can be adjusted in the edge interrupt count register, as necessary, applicable only when int is set to be edge-active; a pulse of a defined width is generated every time int is active. bits 15 to 0 of the edge interrupt count register will define the int pulse width. the maximum pulse width that can be programmed is ffffh, corresponding to a 1 ms pulse width. this setting is necessary for certain processors that may require a different minimum int pulse width than the default value. the default int width set at power-on is about 500 ns. bits 31 to 24 of the edge interrupt count register define the minimum interval between two interrupts to avoid frequent int received by the cpu. the default value of 00h attributed to these bits determines the normal int generation, without any delay. when a delay is programmed and the int becomes active after that delay, several int events may already have occurred. all the interrupt events are represented by the respective bits allocated in the hcinterrupt register. there is no mechanism to show the order or the moment occurrence of an interrupt. the asserted bits in the hcinterrupt register can be cleared by writing back the same value to the hcinterrupt register. this means that writing logic 1 to each of the set bits will reset those bits to the initial inactive state. the int generation rules that apply according to the preceding settings are: ? if an interrupt event occurs but the corresponding bit in the hcinterruptenable register is not set, then the corresponding hcinterrupt register bit is set but the interrupt signal is not asserted. an interrupt will be generated when interrupt is enabled and the source is set. ? for a level-trigger, an interrupt signal remains asserted until the processor clears the hcinterrupt register by writing logic 1 to clear the hcinterrupt register bits that are set. ? if an interrupt is made edge-sensitive and is asserted, writing to clear the hcinterrupt register will not have any effect because the interrupt will be asserted for a prescribed number of clock cycles. ? the clock stopping mechanism does not affect the generation of an interrupt. this is useful during the suspend and resume cycles, when an interrupt is generated to signal a wake-up event. the int generation can also be conditioned by programming the irq mask or and irq mask and registers. with the help of the irq mask and and irq mask or registers for each type of transfer, the software can determine which ptds get priority and an interrupt will be generated when the and or or conditions are met. the ptds that are set will wait until the respective bits of the remaining ptds are set and then all ptds generate an interrupt request to the cpu together. the registers definition shows that the and or or conditions are applicable to the same category of ptds: iso, int, and atl. when an int is generated, the ptd done map registers and the respective v bits will show which ptds were completed.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 24 of 135 isp1763a hi-speed usb otg controller the rules that apply to irq mask and or irq mask or settings are: ? the or mask has a higher priority over the and mask. an int is generated if bit n of the done map is set and the corresponding bit n of the or mask register is set. ? if the or mask for any done bit is not set, then the and mask comes into picture. an int is generated if all the corresponding done bits of the and mask register are set. for example: if bits 2, 4, and 10 are set in the and mask register, an int is generated only if bits 2, 4, and 10 of done map are set. ? if using the int interval setting for the bulk ptd, an interrupt will only occur at the regular time interval as programmed in the atl done timeout register. even if an interrupt occurs before the time-out of the register, no int will be generated until the time is up. example : using irq mask and or irq mask or, without atl timeout register. the and function: activate the int only if ptds 1, 2, and 4 are done. the or function: if any of the ptds 7, 8, or 9 are done, an int for each of the ptds will be raised. 8.10 usb peripheral controller 8.10.1 introduction the design of the peripheral controller in the isp1763a is compatible with the isp1582 hi-speed universal serial bus peripheral controller ic. the functionality of the peripheral controller in the isp1763a is similar to the isp1582. in addition, the register sets are similar, with only a few variations. the usb chapter 9 protocol handling and data transfer operation of the peripheral controller are executed using an external firmware. the external microcontroller or microprocessor can access the peripheral controller-specific registers through the local bus interface. the transfer of data between a microprocessor and the peripheral controller can be done in pio mode. table 8. using the irq mask and or irq mask or registers ptd and register or register time ptd done int 1101ms1- 210-1- 300--- 4 1 0 3 ms 1 active because of and 500--- 600--- 7 0 1 5 ms 1 active because of or 8 0 1 6 ms 1 active because of or 9 0 1 7 ms 1 active because of or
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 25 of 135 isp1763a hi-speed usb otg controller 8.10.2 peripheral controller data transfer operation the following sections explain how the peripheral controller in the isp1763a handles an in data transfer and an out data transfer. an in data transfer means transfer from the isp1763a to an external usb host, through the upstream port. an out transfer means transfer from an external usb host to the isp1763a. in peripheral mode, the isp1763a acts as a usb peripheral. 8.10.2.1 in data transfer ? the arrival of the in token is detected by the serial interface engine (sie) by decoding the packet identifier (pid). ? the sie also checks the device number and the endpoint number to verify whether they are okay. ? if the endpoint is enabled, the sie checks the endpoint status. if the endpoint is full and data in the buffer is validated, the contents of the buffer memory are sent during the data phase; else an nak handshake is sent. ? after the data phase, the sie expects a handshake (ack) from the host, except for iso endpoints. ? on receiving the handshake (ack), the sie updates the contents of the endpoint status and interrupt registers, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is sent because there is no handshake phase. ? on receiving an interrupt, the microprocessor reads the dcinterrupt register. it knows which endpoint has generated the interrupt. if the buffer is empty, it fills up the buffer so that data can be sent by the sie at the next in token phase. 8.10.2.2 out data transfer ? the arrival of the out token is detected by the sie by decoding the pid. ? the sie checks the device and endpoint numbers to verify whether they are okay. ? if the endpoint is enabled, the sie checks the status of the endpoint. if the endpoint is empty, data from the usb host is stored in the buffer memory during the data phase, else a nak handshake is sent. ? after the data phase, the sie sends a handshake (ack) to the host, except for iso endpoints. ? the sie updates the endpoint status and interrupt registers, which in turn generates an interrupt to the microprocessor. for iso endpoints, the dcinterrupt register is updated as soon as data is received because there is no handshake phase. ? on receiving an interrupt, the microprocessor reads the dcinterrupt register. it knows which endpoint has generated the interrupt. if the buffer is full, it empties the buffer so that data can be received by the sie at the next out token phase. 8.10.3 endpoint description each usb peripheral is logically composed of several independent endpoints. an endpoint acts as a terminus of a communication flow between the usb host and the usb device. at design time, each endpoint is assigned a unique endpoint identifier, see ta b l e 9 . the combination of the peripheral address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 26 of 135 isp1763a hi-speed usb otg controller uniquely referenced. the peripheral controller has 4 kb of internal fifo memory, which is shared among the enabled usb endpoints. the two control endpoints are fixed 64 bytes long. any of the seven in and seven out endpoints can separately be enabled or disabled. the endpoint type (interrupt, isochronous, or bulk) and packet size of these endpoints can individually be configured, depending on the requirements of the application. optional double buffering increases the data throughput of these data endpoints. 8.10.4 peripheral controller suspend the peripheral controller in the isp1763a detects a usb suspend when constant idle state is present on the usb bus for 3 ms. the steps leading the peripheral controller to the suspend state are as follows: 1. if there is no sof for 3 ms, the peripheral controller in the isp1763a sets bit susp of the dcinterrupt register. this will generate an interrupt if bit iesusp of the dcinterruptenable register is set. 2. when the firmware detects a suspend condition through bit iesusp, it must prepare all system components for the suspend state. 3. in the interrupt service routine, the firmware must check the current status of the usb bus. when bit vbusstat of the mode register is logic 0, the usb bus has left suspend mode and the process must be aborted. otherwise, the next step can be executed. 4. to meet the suspend current requirements for a bus-powered device, internal clocks must be switched off by clearing bit clkaon of the mode register. table 9. endpoint access and programmability endpoint identifier maximum packet size double buffering endpoint type direction ep0rx 64 bytes (fixed) no control out out ep0tx 64 bytes (fixed) no control in in ep1rx programmable yes programmable out ep1tx programmable yes programmable in ep2rx programmable yes programmable out ep2tx programmable yes programmable in ep3rx programmable yes programmable out ep3tx programmable yes programmable in ep4rx programmable yes programmable out ep4tx programmable yes programmable in ep5rx programmable yes programmable out ep5tx programmable yes programmable in ep6rx programmable yes programmable out ep6tx programmable yes programmable in ep7rx programmable yes programmable out ep7tx programmable yes programmable in
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 27 of 135 isp1763a hi-speed usb otg controller 5. when the firmware has set and cleared the gosusp bit of the mode register, the peripheral controller in the isp1763a enters the suspend state. a flag must be set by the firmware to indicate that the peripheral controller is in the suspend state. the peripheral controller in the isp1763a will remain in the suspend state for at least 5 ms, before responding to wake-up events, such as global resume or chip select active. 8.10.5 peripheral controller resume wake-up from the suspend state is initiated either by the usb host or by the application: ? usb host: drives a k-state on the usb bus (global resume). ? application: remote wake-up using a low pulse on pins cs_n/ce_n and rd_n/ds_n/re_n/oe_n, if enabled using bit wkupcs of the mode register. the steps of a wake-up sequence are as follows: 1. the internal oscillator and the pll multiplier are re-enabled. when stabilized, clock signals are routed to all internal circuits of the peripheral controller in the isp1763a. 2. the resume bit of the dcinterrupt register is set. this will generate an interrupt if bit ieresm of the dcinterruptenable register is set. 3. the peripheral controller in the isp1763a resumes its normal functionality 5 ms after starting the wake-up sequence. the firmware can clear its suspend state flag at this point. 4. after resume, the internal registers of the peripheral controller in the isp1763a are write-protected to prevent corruption by inadvertent writing during power-up of external components. the firmware must send an unlock device command to the peripheral controller in the isp1763a to restore its full functionality. 8.10.6 remote wake-up in a remote wake-up to the host, the firmware must set and clear the sndrsu bit of the mode register. the peripheral controller in the isp1763a will drive a resume signal (a k-state) on the usb bus for 10 ms after a 5 ms delay. 8.11 phase-locked loop (pll) clock multiplier the internal pll supports 12 mhz, 19.2 mhz, or 24 mhz input, which can be a crystal or a clock already existing in the system. the frequency selection can be done using the freqsel1 and freqsel2 pins. no external components are required for the pll operation. 8.12 power management the isp1763a is mainly designed for mobile applications that require more precision power saving control to achieve extremely low power consumption. it implements a flexible power management scheme that allows various stages of power saving. 8.12.1 power supply power supplies are defined in ta b le 1 0 .
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 28 of 135 isp1763a hi-speed usb otg controller 8.12.2 power modes 8.12.2.1 operation mode all power supplies are present. consists of host mode, peripheral mode, and idle mode. 8.12.2.2 suspend mode all power supplies are present. possible defined states are host-only suspend, peripheral-only suspend, or both. for the peripheral suspend procedure, see section 8.10.4 . the steps for the host suspend are as follows: 1. clear the rs bit of the usbcmd register to stop the host controller from executing schedule. 2. set the susp bit and clear the fpr bit of the portsc1 register to force the host controller to go into suspend. 8.12.2.3 deep sleep mode all power supplies are present. regulator is in suspend mode. the clocks of the host controller and the peripheral controller are turned off. the steps to enter deep sleep mode are: 1. the peripheral must be in suspend state or disabled. see section 8.10.4 . 2. clear the rs bit of the usbcmd register to stop the host controller from executing schedule. 3. clear the clkaon bit in the mode register to save power. 4. set the reg_pwr and reg_susp_pwr bits of the power down control register to logic 1 to force the regulator to go into suspend mode. 8.12.2.4 power-down mode the regulator is powered down. the isp1763a has no functionality. the isp1763a can be woken up by a dummy read signal, that is, both rd_n/ds_n/re_n/oe_n and cs_n/ce_n are active low. the isp1763a enters power-down mode when any of the following conditions is met: ? bit reg_pwr of the power down control register is set to logic 0. ? reset_n is asserted. 8.12.2.5 isp1763a wake up the regulator will be in normal operating mode and the clock will be enabled when either of these conditions are triggered: table 10. power supply symbol voltage range description v cc(i/o) 1.65 v to 1.95 v or 3.0 v to 3.6 v supply for the i/o pad v cc(3v3) 3.0 v to 3.6 v supply for usb transceivers, cores, and analog modules
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 29 of 135 isp1763a hi-speed usb otg controller ? application: dummy read access with a low pulse on pins cs_n/ce_n and rd_n/ds_n/re_n/oe_n. ? host: remote wake up from the external usb device. ? host: v bus overcurrent condition triggered on the system. ? peripheral: resume signaling received from the external usb host. 8.12.2.6 isolation mode all power supplies are not present. although v bus may be present, it will not activate the chip or damage it. 8.12.3 power-up and reset sequence when v cc(i/o) and v cc(3v3) are on, it is recommended that the system generates a reset_n pulse to ensure that the isp1763a regulator is in the power-down state. the regulator will be powered on when the system generates a dummy read (ignore return value) access to the isp1763a. an internal por pulse will be generated during the regulator powers on, so that internal circuits are in reset state after the regulator power is stable. 8.12.4 atx reference voltage the atx circuit provides a stable internal voltage reference to bias the analog circuitry. this circuit requires an accurate external reference resistor. connect 12 k ? 1% resistor between pins rref1, rref2, and gnd. (1) dummy read. fig 8. power-up and reset sequence 004aa085 v cc(i/o) v cc(3v3) reset_n cs_n/ce_n r d_n/ds_n/ re_n/oe_n v reg(1v2) i nternal por t opr_rd(dmy_rd) t dmy_rd(reset_n) t dmy_rd(reset) (1) (1)
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 30 of 135 isp1763a hi-speed usb otg controller 9. otg controller-specific registers [1] the r/s/c access type represents a field that can be read, set, or cleared (set to 0). a set register is used to configure t he function that is defined in the bit field of the register. the clear register is used to clear the configuration setting. logic 1 in a bit fie ld clears the function that is defined by the bit in the set register. 9.1 otg control register 9.1.1 otg control register ta b l e 1 2 shows the bit allocation of the register. table 11. overview of otg controller-specific registers address register reset value access [1] reference otg control register set ? e4h clear ? e6h otg control 8086h r/s/c section 9.1.1 on page 30 otg interrupt registers e8h otg interrupt source 1188h r section 9.2.1 on page 31 set ? ech clear ? eeh otg interrupt latch 0000h r/s/c section 9.2.2 on page 32 set ? f0h clear ? f2h otg interrupt enable fall 0000h r/s/c section 9.2.3 on page 33 set ? f4h clear ? f6h otg interrupt enable rise 0000h r/s/c section 9.2.4 on page 34 otg timer register timer_low_word_set ? f8h timer_low_word_clear ? fah timer_high_word_set ? fch timer_high_word_clear ? feh otg timer 0000h r/s/c section 9.3.1 on page 35 table 12. otg_ctrl - otg control register (address set: e4h, clear: e6h) bit allocation bit 15 14 13 12 11 10 9 8 symbol hc_2_dis reserved tmr_sel reserved otg_ disable otg_se0_ en bdis_ acon_en reset 10000000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c bit 7 6 5 4 3 2 1 0 symbol sw_sel_ hc_dc vbus_ chrg vbus_ dischrg vbus_ drv reserved dm_pull down dp_pull down dp_pull up reset 10000110 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 31 of 135 isp1763a hi-speed usb otg controller 9.2 otg interrupt registers 9.2.1 otg interrupt source register this register indicates the current state of the signals that can generate an interrupt. the bit allocation of the register is given in ta b l e 1 4 . table 13. otg_ctrl - otg control register (address set: e4h, clear: e6h) bit description bit symbol description 15 hc_2_dis 0 ? port 2 is enabled as host. 1 ? port 2 is disabled. 14 - reserved 13 tmr_sel port 1 peripheral suspend timer select 0 ? 3.1 ms 1 ? 3.0 ms 12 to 11 - reserved 10 otg_disable 0 ? otg functionality is enabled. 1 ? otg disabled; pure host or peripheral. 9 otg_se0_en this bit is used by the host controller to send se0 on remote connect. 0 ? no se0 sent on remote connect detection. 1 ? se0 (bus reset) sent on remote connect detection. remark: this bit is normally set when the b-device goes into the b_wait_acon state (recommended sequence: loc_conn = 0 delay 0ms otg_se0_en = 1 sel_hc_dc = 0) and is cleared when it comes out of the b_wait_acon state. 8 bdis_acon_en enables the a-device to connect if the b-device disconnect is detected. 7 sw_sel_hc_dc in software hnp mode, this bit selects between the host controller and the peripheral controller. 0 ? host controller is connected to atx. 1 ? peripheral controller is connected to atx. this bit is set to logic 1 by the hardware when there is an event corresponding to the bdis_acon interrupt. bdis_acon_en is set and there is an automatic pull-up connection on remote disconnect. 6 vbus_chrg connect v bus to v cc(3v3) through a resistor. 5 vbus_dischrg discharge v bus to ground through a resistor. 4 vbus_drv in otg mode, setting this bit will turn on port 1 power. in non-otg mode, setting this bit does not have any effect and v bus is controlled using the hub command. 3 - reserved 2dm_pulldown 0 ? disable dm pull-down 1 ? enable dm pull-down 1 dp_pulldown 0 ? disable dp pull-down 1 ? enable dp pull-down 0 dp_pullup 0 ? the pull-up resistor is disconnected from the dp line. 1 ? an internal 1.5 k pull-up resistor is present on the dp line.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 32 of 135 isp1763a hi-speed usb otg controller 9.2.2 otg interrupt latch register the otg interrupt latch register indicates the source that generated the interrupt. the status of this register bits depends on the settings of the interrupt enable fall and interrupt enable rise registers, and the occurrence of the respective events. the bit allocation of the register is given in table 16 . table 14. otg_intr_src - otg interrupt source register (address e8h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved dp2_srp p2_a_ sess_vld otg_tmr_ timeout b_se0_ srp reset 00010001 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol b_sess_ end reserved rmt_ conn id dp_srp a_b_ sess_vld vbus_vld reset 10001000 access rrrrrrrr table 15. otg_intr_src - otg interrupt source register (address e8h) bit description bit symbol description 15 to 12 - reserved 11 dp2_srp detects the dp2 pin status. 10 p2_a_sess_vld reflects the voltage on pin oc2/v bus2 is above the a-device session valid threshold. 9 otg_tmr_timeout reflects the otg timer timeout. 8 b_se0_srp detects 2 ms of se0 in the b-device idle state. 7 b_sess_end reflects the voltage on pin oc1/v bus1 is below the b-device session end threshold. 6 to 5 - reserved 4 rmt_conn reflects remote connection is detected. 3 id reflects the id pin status. 2 dp_srp detects the dp1 pin status. 1 a_b_sess_vld reflects the voltage on pin oc1/v bus1 is above the a-device session valid threshold for the a-device. reflects the voltage on pin oc1/v bus1 is above the b-device session valid threshold for the b-device. 0 vbus_vld reflects the voltage on pin oc1/v bus1 is above the a-device v bus valid threshold. table 16. otg_intr_l - otg interrupt latch register (address set: ech, clear: eeh) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved dp2_srp _l p2_a_ sess_vld_l otg_tmr_ timeout_l b_se0_ srp_l reset 000000 00 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c bit 7 6 5 4 3 2 1 0 symbol b_sess_ end_l bdis_ acon_l reserved rmt_ conn_l id_l dp_srp_l a_b_sess _vld_l vbus_vld _l reset 000000 00 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 33 of 135 isp1763a hi-speed usb otg controller 9.2.3 otg interrupt enable fall register ta b l e 1 8 shows the bit allocation of this register that enables interrupts on transition from logic 1 to logic 0. table 17. otg_intr_l - otg interrupt latch register (address set: ech, clear: eeh) bit description bit symbol description 15 to 12 - reserved 11 dp2_srp_l set when an unmasked event occurs on dp2_srp. 10 p2_a_sess_vld_l set when an unmasked event occurs on p2_a_sess_vld. 9 otg_tmr_timeout_l set when an unmasked event occurs on otg_tmr_timeout. 8 b_se0_srp_l set when an unmasked event occurs on b_se0_srp. 7 b_sess_end_l set when an unmasked event occurs on b_sess_end. 6 bdis_acon_l set when an unmasked event occurs on bdis_acon. 5 - reserved 4 rmt_conn_l set when an unmasked event occurs on rmt_conn. 3 id_l set when an unmasked event occurs on id. 2 dp_srp_l set when an unmasked event occurs on dp_srp. 1 a_b_sess_vld_l set when an unmasked event occurs on a_b_sess_vld. 0 vbus_vld_l set when an unmasked event occurs on vbus_vld. table 18. otg_intr_en_f - otg interrupt enable fall regi ster (address set: f0h, clear: f2h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved dp2_srp_ en_f p2_a_sess _vld_en_f otg_tmr _timeout _en_f b_se0_ srp_en_f reset 00000 000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c bit 7 6 5 4 3 2 1 0 symbol b_sess_ end_en_f bdis_ acon_en_ f reserved rmt_ conn_en _f id_en_f dp_srp_ en_f a_b_sess _vld_en_ f vbus_vld _en_f reset 00000000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c table 19. otg_intr_en_f - otg interrupt enable fall regi ster (address set: f0h, clear: f2h) bit description bit symbol description 15 to 12 - reserved 11 dp2_srp_en_f enable interrupt when port 2 dp transitions from logic 1 to logic 0. 10 p2_a_sess_vld_en_f enable interrupt when port 2 a_sess_vld transitions from logic 1 to logic 0 for the a-device. 9 otg_tmr_timeout_en_f enable interrupt on otg timer time-out transition from logic 1 to logic 0. 8 b_se0_srp_en_f enable interrupt when b_se0_srp transitions from logic 1 to logic 0. 7 b_sess_end_en_f enable interrupt when v bus session end transitions from logic 1 to logic 0. 6 bdis_acon_en_f enable interrupt when bdis_acon transitions from logic 1 to logic 0. 5 - reserved
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 34 of 135 isp1763a hi-speed usb otg controller 9.2.4 otg interrupt enable rise register this register (see ta b le 2 0 for bit allocation) enables interrupts on transition from logic 0 to logic 1. 4 rmt_conn_en_f enable interrupt when rmt_conn transitions from logic 1 to logic 0. 3 id_en_f enable interrupt when id transitions from logic 1 to logic 0. 2 dp_srp_en_f enable interrupt when port 1 dp transitions from logic 1 to logic 0. 1 a_b_sess_vld_en_f enable interrupt when ab-session valid transitions from logic 1 to logic 0. 0 vbus_vld_en_f enable interrupt when vbus_vld transitions from logic 1 to logic 0. table 19. otg_intr_en_f - otg interrupt enable fall regi ster (address set: f0h, clear: f2h) bit description bit symbol description table 20. otg_intr_en_r - otg interrupt enable rise register (address set: f4h, clear: f6h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved dp2_srp _en_r p2_a_sess _vld_en_r otg_tmr_ timeout_ en_r b_se0_ srp_en_r reset 000000 00 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c bit 7 6 5 4 3 2 1 0 symbol b_sess_ end_en_ r bdis_ acon_en _r reserved rmt_ conn_en _r id_en_r dp_srp_ en_r a_b_sess _vld_en_ r vbus_vld _en_r reset 00000000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c table 21. otg_intr_en_r - otg interrupt enable rise register (address set: f4h, clear: f6h) bit description bit symbol description 15 to 12 - reserved 11 dp2_srp_en_r enable interrupt when port 2 dp transitions from logic 0 to logic 1. 10 p2_a_sess_vld_en_r enable interrupt when port 2 a_sess_vld transitions from logic 0 to logic 1 for the a-device. 9 otg_tmr_timeout_en_r enable interrupt on otg timer time-out transition from logic 0 to logic 1. 8 b_se0_srp_en_r enable interrupt when b_se0_srp transitions from logic 0 to logic 1. 7 b_sess_end_en_r enable interrupt when v bus session end transitions from logic 0 to logic 1. 6 bdis_acon_en_r enable interrupt when bdis_acon transitions from logic 0 to logic 1. 5 - reserved 4 rmt_conn_en_r enable interrupt when rmt_conn transitions from logic 0 to logic 1. 3 id_en_r enable interrupt when id transitions from logic 0 to logic 1. 2 dp_srp_en_r enable interrupt when port 1 dp transitions from logic 0 to logic 1. 1 a_b_sess_vld_en_r enable interrupt when ab-session valid transitions from logic 0 to logic 1. 0 vbus_vld_en_r enable interrupt when vbus_vld transitions from logic 0 to logic 1.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 35 of 135 isp1763a hi-speed usb otg controller 9.3 otg timer register 9.3.1 otg timer register this is a 32-bit register organized as two 16-bit fields. these two fields have separate set and clear addresses. table 22 shows the bit allocation of the register. table 22. otg_tmr - otg timer register (address low word set: f8h, low word clear: fah; high word set: fch, high word clear: feh) bit allocation bit 31 30 29 28 27 26 25 24 symbol start_ tmr reserved reset 00000000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c bit 23 22 21 20 19 18 17 16 symbol timer_init_value[23:16] reset 00000000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c bit 15 14 13 12 11 10 9 8 symbol timer_init_value[15:8] reset 00000000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c bit 7 6 5 4 3 2 1 0 symbol timer_init_value[7:0] reset 00000000 access r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c r/s/c table 23. otg_tmr - otg timer register (address low word set: f8h, low word clear: fah; high word set: fch, high word clear: feh) bit description bit symbol description 31 start_tmr this is the start/stop bit of the otg timer. writing logic 1 will cause the otg timer to load tmr_init_value into the counter and start to count. writing logic 0 will stop the timer. this bit is automatically cleared when the otg timer is timed out. 0 ? stop the timer. 1 ? start the timer. 30 to 24 - reserved 23 to 0 timer_init_ value[23:0] these bits define the initial value used by the otg timer. the timer interval is 0.01 ms. maximum time allowed is 167.772 s.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 36 of 135 isp1763a hi-speed usb otg controller 10. host controller-specific registers ta b l e 2 4 shows the bit description of the host controller-specific registers. table 24. overview of host controller-specific registers address register reset value references ehci operational registers 8ch usbcmd 0000 0000h section 10.1.1 on page 37 90h usbsts 0000 0000h section 10.1.2 on page 37 94h usbintr 0000 0000h section 10.1.3 on page 38 98h frindex 0000 0000h section 10.1.4 on page 39 9ch configflag 0000 0000h section 10.1.5 on page 40 a0h portsc1 0000 2000h section 10.1.6 on page 41 a4h iso ptd done map 0000h section 10.1.7 on page 42 a6h iso ptd skip map ffffh section 10.1.8 on page 42 a8h iso ptd last ptd 0000h section 10.1.9 on page 43 aah int ptd done map 0000h section 10.1.10 on page 43 ach int ptd skip map ffffh section 10.1.11 on page 43 aeh int ptd last ptd 0000h section 10.1.12 on page 43 b0h atl ptd done map 0000h section 10.1.13 on page 44 b2h atl ptd skip map ffffh section 10.1.14 on page 44 b4h atl ptd last ptd 0000h section 10.1.15 on page 44 configuration registers b6h hw mode control 0000h section 10.2.1 on page 45 b8h sw reset 0000h section 10.2.2 on page 46 bah hcbufferstatus 0000h section 10.2.3 on page 47 bch hcdmaconfiguration 0000h section 10.2.4 on page 48 c0h atl done timeout 0000 0000h section 10.2.5 on page 49 c4h memory 0000h section 10.2.6 on page 49 c6h data port 0000h section 10.2.7 on page 50 c8h edge interrupt count 0000 000fh section 10.2.8 on page 50 60h dma data port - section 10.2.9 on page 51 cch dma start address 0000h section 10.2.10 on page 51 d0h power down control 03e8 1ba0h section 10.2.11 on page 51 interrupt registers d4h hcinterrupt 0040h section 10.3.1 on page 53 d6h hcinterruptenable 0000h section 10.3.2 on page 55 d8h iso irq mask or 0000h section 10.3.3 on page 57 dah int irq mask or 0000h section 10.3.4 on page 57 dch atl irq mask or 0000h section 10.3.5 on page 57 deh iso irq mask and 0000h section 10.3.6 on page 57 e0h int irq mask and 0000h section 10.3.7 on page 58 e2h atl irq mask and 0000h section 10.3.8 on page 58
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 37 of 135 isp1763a hi-speed usb otg controller 10.1 ehci operational registers 10.1.1 usbcmd register the usb command (usbcmd) register indicates the command to be executed by the serial host controller. writing to this register causes a command to be executed. ta b l e 2 5 shows the usbcmd register bit allocation. [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to enhanced host controller interface specification for universal serial bus rev. 1.0 . 10.1.2 usbsts register the usb status (usbsts) register indicates pending interrupts and various states of the host controller. the status resulting from a transaction on the serial bus is not indicated in this register. the software clears register bits by writing ones to them. the bit allocation is given in table 27 . table 25. usbcmd - usb command register (address 8ch) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lhcr reserved [1] fls[1:0] hcreset rs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 26. usbcmd - usb command register (address 8ch) bit description bit symbol description [1] 31 to 8 - reserved 7 lhcr light host controller reset : it allows the driver software to reset the ehci controller without affecting the state of the ports or the relationship to the companion host controllers. to reset, write a one followed by a zero. 6 to 4 - reserved 3 to 2 fls[1:0] frame list size : default 00b. this field specifies the size of the frame list. 1 hcreset host controller reset : this control bit is used by the software to reset the host controller. the software writes one to this bit to reset. this bit is set to zero by the host controller when the reset process is complete. 0rs run/stop : 1 = run, 0 = stop. when set, the host controller executes the schedule.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 38 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to enhanced host controller interface specification for universal serial bus rev. 1.0 . 10.1.3 usbintr register the usb interrupt (usbintr) bit allocation is given in table 29 . table 27. usbsts - usb status register (address 90h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] flr pcd reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 28. usbsts - usb status register (address 90h) bit description bit symbol description [1] 31 to 4 - reserved 3flr frame list rollover : the host controller sets this bit to logic 1 when the frame list index rolls over from its maximum value to logic 0. the exact value at which the rollover occurs depends on the fls bits. 2pcd port change detect : the host controller sets this bit to logic 1 when any port, where the po bit is set to zero, has a bit transition from zero to one or the fpr bit transitions from zero to one as a result of a j-k transition detected on a suspended port. 1 to 0 - reserved table 29. usbintr - usb interrupt register (address 94h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 39 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to enhanced host controller interface specification for universal serial bus rev. 1.0 . 10.1.4 frindex register the frame index (frindex) register is used by the host controller to index into the periodic frame list. the register updates every 125 s (once each microframe). bits n to 3 are used to select a particular entry in the periodic frame list during periodic schedule execution. this register must be written as a double word. a byte or word write produces undefined results. this register must be written as a double word. a write to this register while the rs (run/stop) bit is set produces undefined results. writes to this register also affect the sof value. the bit allocation is given in table 31 . bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] flr_ie pcd_ie reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 30. usbintr - usb interrupt register (address 94h) bit description bit symbol description [1] 31 to 4 - reserved 3 flr_ie frame list rollover interrupt enable : when this bit is logic 1, and the frame list rollover bit in the usbsts register is logic 1, the host controller will issue an interrupt. the interrupt is acknowledged by the software clearing the frame list rollover bit. 2 pcd_ie port change detect interrupt enable : when this bit is logic 1, and the port change detect bit in the usbsts register is logic 1, the host controller will issue an interrupt. the interrupt is acknowledged by the software clearing the port change detect bit. 1 to 0 - reserved table 31. frindex - frame index register (address: 98h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 40 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. [1] for details on register bit description, refer to enhanced host controller interface specification for universal serial bus rev. 1.0 . 10.1.5 configflag register the bit allocation of the configure flag (configflag) register is given in table 33 . [1] the reserved bits should always be written with the reset value. bit 15 14 13 12 11 10 9 8 symbol reserved [1] frindex[13:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol frindex[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 32. frindex - frame index register (address: 98h) bit description bit symbol description [1] 31 to 14 - reserved 13 to 0 frindex[13:0] frame index : bits in this register are used for the frame number in the sof packet and as the index into the frame list. the value in this register increments at the end of each time frame. table 33. configflag - configure flag register (address 9ch) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] cf reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 41 of 135 isp1763a hi-speed usb otg controller [1] for details on register bit description, refer to enhanced host controller interface specification for universal serial bus rev. 1.0 . 10.1.6 portsc1 register the port status and control (portsc) register (bit allocation: table 35 ) is in the power well. it is reset by the hardware only when the auxiliary power is initially applied or in response to a host controller reset. the initial conditions of a port are: ? no peripheral connected ? port disabled if the port has power control, the software cannot change the state of the port until it sets port power bits. the software must not attempt to change the state of the port until the power is stable on the port (maximum delay is 20 ms from the transition). [1] the reserved bits should always be written with the reset value. table 34. configflag - configure flag register (address 9ch) bit description bit symbol description [1] 31 to 1 - reserved 0cf configure flag : the host software sets this bit as the last action when it is configuring the host controller. this bit controls the default port-routing control logic. table 35. portsc1 - port status and control 1 register (address a0h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] ptc[3:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol reserved [1] po pp ls[1:0] reserved [1] pr reset 00100000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol susp fpr reserved [1] ped ecsc eccs reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 36. portsc1 - port status and control 1 register (address a0h) bit description bit symbol description [1] 31 to 20 - reserved 19 to 16 ptc[3:0] port test control : when this field is zero, the port is not operating in test mode. a non-zero value indicates that it is operating in test mode indicated by the value. 15 to 14 - reserved
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 42 of 135 isp1763a hi-speed usb otg controller [1] for details on register bit description, refer to enhanced host controller interface specification for universal serial bus rev. 1.0 . [2] these fields read logic 0, if the pp (port power) bit in register portsc1 is logic 0. 10.1.7 iso ptd done map register the bit description of the register is given in ta b le 3 7 . this register represents a direct map of the done status of 16 ptds. the bit corresponding to a particular ptd will be set to logic 1 as soon as that ptd execution is completed. reading the done map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of the new executed ptds. 10.1.8 iso ptd skip map register ta b l e 3 8 shows the bit description of the register. 13 po port owner : this bit unconditionally goes to logic 0 when the configured bit in the configflag register makes a logic 0 to logic 1 transition. this bit unconditionally goes to logic 1 whenever the configured bit is logic 0. 12 pp port power : this bit will enable the root hub for the upstream port. 11 to 10 ls[1:0] line status : this field reflects current logical levels of the dp (bit 11) and dm (bit 10) signal lines. 9 - reserved 8pr port reset : write logic 1 to this bit to reset the bus. write logic 0 to this bit to terminate the bus reset sequence. [2] 7susp suspend : logic 1 means the port is in the suspend state. logic 0 means the port is not suspended. [2] 6fpr force port resume : logic 1 means resume detected or driven on the port. logic 0 means no resume (k-state) detected or driven on the port. [2] 5 to 3 - reserved 2 ped port enabled/disabled : logic 1 means enable. logic 0 means disable. [2] 1ecsc connect status change : logic 1 means change in eccs. logic 0 means no change. [2] 0 eccs current connect status : logic 1 indicates a peripheral is present on the port. logic 0 indicates no device is present. [2] table 36. portsc1 - port status and control 1 register (address a0h) bit description ?continued bit symbol description [1] table 37. iso ptd done map register (address a4h) bit description legend: * reset value bit symbol access value description 15 to 0 iso_ptd_done_ map[15:0] r 0000h* iso ptd done map : done map for each of the 16 ptds for the iso transfer. table 38. iso ptd skip map register (address a6h) bit description legend: * reset value bit symbol access value description 15 to 0 iso_ptd_skip_ map[15:0] r/w ffffh* iso ptd skip map : skip map for each of the 16 ptds for the iso transfer.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 43 of 135 isp1763a hi-speed usb otg controller when a bit in the ptd skip map is set to logic 1, that ptd will be skipped although its v bit may be set. the information in that ptd is not processed. when the ptd is in process, the software must not set this bit. after writing to this register, add 100 ns delay before reading it. 10.1.9 iso ptd last ptd register ta b l e 3 9 shows the bit description of the iso ptd last ptd register. once the lastptd bit corresponding to a ptd is set, this will be the last ptd processed (checking v = 1) in that ptd category. subsequently, processing will restart with the first ptd of that group. this is useful to reduce the time in which all the ptds, the respective memory space, would be checked, especially if only a few ptds are defined. 10.1.10 int ptd done map register the bit description of the register is given in ta b le 4 0 . this register represents a direct map of the done status of 16 ptds. the bit corresponding to a particular ptd will be set to logic 1 as soon as that ptd execution is completed. reading the done map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of the new executed ptds. 10.1.11 int ptd skip map register ta b l e 4 1 shows the bit description of the int ptd skip map register. when a bit in the ptd skip map is set to logic 1, that ptd will be skipped although its v bit may be set. the information in that ptd is not processed. when the ptd is in process, the software must not set this bit. after writing to this register, add 100 ns delay before reading it. 10.1.12 int ptd last ptd register the bit description of the register is given in ta b le 4 2 . table 39. iso ptd last ptd register (address a8h) bit description legend: * reset value bit symbol access value description 15 to 0 iso_ptd_last_ ptd[15:0] r/w 0000h* iso ptd last ptd : last ptd of the 16 ptds. 1h ? one ptd in iso. 2h ? two ptds in iso. 4h ? three ptds in iso. table 40. int ptd done map register (address aah) bit description legend: * reset value bit symbol access value description 15 to 0 int_ptd_done_ map[15:0] r 0000h* int ptd done map : done map for each of the 16 ptds for the int transfer. table 41. int ptd skip map register (address ach) bit description legend: * reset value bit symbol access value description 15 to 0 int_ptd_skip_ map[15:0] r/w ffffh* int ptd skip map : skip map for each of the 16 ptds for the int transfer.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 44 of 135 isp1763a hi-speed usb otg controller once the lastptd bit corresponding to a ptd is set, this will be the last ptd processed (checking v = 1) in that ptd category. subsequently, processing will restart with the first ptd of that group. this is useful to reduce the time in which all the ptds, the respective memory space, would be checked, especially if only a few ptds are defined. 10.1.13 atl ptd done map register ta b l e 4 3 shows the bit description of the atl ptd done map register. this register represents a direct map of the done status of 16 ptds. the bit corresponding to a particular ptd will be set to logic 1 as soon as that ptd execution is completed. reading the done map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of the new executed ptds. 10.1.14 atl ptd skip map register the bit description of the register is given in ta b le 4 4 . when a bit in the ptd skip map is set to logic 1, that ptd will be skipped although its v bit may be set. the information in that ptd is not processed. when the ptd is in process, the software must not set this bit. after writing to this register, add 100 ns delay before reading it. 10.1.15 atl ptd last ptd register the bit description of the atl ptd last ptd register is given in table 45 . table 42. int ptd last ptd register (address aeh) bit description legend: * reset value bit symbol access value description 15 to 0 int_ptd_last_ ptd[15:0] r/w 0000h* int ptd last ptd : last ptd of the 16 ptds. 1h ? one ptd in int. 2h ? two ptds in int. 3h ? three ptds in int. table 43. atl ptd done map register (address b0h) bit description legend: * reset value bit symbol access value description 15 to 0 atl_ptd_done_ map[15:0] r 0000h* atl ptd done map : done map for each of the 16 ptds for the atl transfer. table 44. atl ptd skip map register (address b2h) bit description legend: * reset value bit symbol access value description 15 to 0 atl_ptd_skip_ map[15:0] r/w ffffh* atl ptd skip map : skip map for each of the 16 ptds for the atl transfer.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 45 of 135 isp1763a hi-speed usb otg controller once the lastptd bit corresponding to a ptd is set, this will be the last ptd processed (checking v = 1) in that ptd category. subsequently, processing will restart with the first ptd of that group. this is useful to reduce the time in which all the ptds, the respective memory space, would be checked, especially if only a few ptds are defined. 10.2 configuration registers 10.2.1 hw mode control register ta b l e 4 6 shows the bit allocation of the register. remark: use single-byte write access when configuring registers in nand or nor 8-bit mode. [1] the reserved bits should always be written with the reset value. table 45. atl ptd last ptd register (address b4h) bit description legend: * reset value bit symbol access value description 15 to 0 atl_ptd_last_ ptd[15:0] r/w 0000h* atl ptd last ptd : last ptd of the 16 ptds. 1h ? one ptd in atl. 2h ? two ptds in atl. 4h ? three ptds in atl. table 46. hw mode control - hardware mode control register (address b6h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] id_pullup dev_dma comn_ int comn_ dma reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] dack_ pol dreq_ pol data_bus _width intf_ lock intr_pol intr_ level global_ intr_en reset 000 00000 access r/w r/w r/w r/w r/w r/w r/w r/w table 47. hw mode control - hardware mode control register (address b6h) bit description bit symbol description 15 to 13 - reserved 12 id_pullup id pull up : connects a pull-up to the id line and enables sampling of the id level. disabling the id line sampler will reduce the phy power consumption. 0 ? disable sampling of the id line. 1 ? enable sampling of the id line. 11 dev_dma device dma : when this bit and bit 9 are set, dc_dreq and dc_dack peripheral signals are routed to the dreq and dack pins. 10 comn_int common int : when this bit is set, dc_int will be routed to the int pin. 9 comn_dma common dma : when this bit and bit 11 are set, the dc_dreq and dc_dack peripheral signals are routed to the dreq and dack pins. 8 to 7 - reserved
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 46 of 135 isp1763a hi-speed usb otg controller 10.2.2 sw reset register ta b l e 4 8 shows the bit allocation of the register. 6 dack_pol dack polarity : 1 ? indicates that the dack input is active high. 0 ? indicates that the dack input is active low. remark: value written to this bit must be the same as the value written to bit dack_pol in the peripheral controller dma hardware register (address 3ch). 5 dreq_pol dreq polarity : 1 ? indicates that the dreq output is active high. 0 ? indicates that the dreq output is active low. remark: value written to this bit must be the same as the value written to bit dreq_pol in the peripheral controller dma hardware register (address 3ch). 4 data_bus_ width data bus width : 0 ? defines a 16-bit data bus width. 1 ? sets a 8-bit data bus width. 3 intf_lock interface lock : 0 ? unlocks the bus interface. 1 ? locks the bus interface. 2 intr_pol interrupt polarity : 0 ? active low 1 ? active high remark: value written to this bit must be the same as the value written to bit intpol in the peripheral controller interrupt configuration register (address 10h). 1 intr_level interrupt level : 0 ? int is level triggered. 1 ? int is edge triggered. the pulse width depends on the no_of_clk bits in the edge interrupt count register. remark: value written to this bit must be the same as the value written to bit intlvl in the peripheral controller interrupt configuration register (address 10h). 0 global_ intr_en global interrupt enable : this bit must be set to logic 1 to enable int signal assertion. 0 ? int assertion disabled. int will never be asserted, regardless of other settings or int events. 1 ? int assertion enabled. int will be asserted according to the hcinterruptenable register, and event setting and occurrence. table 47. hw mode control - hardware mode control register (address b6h) bit description ?continued bit symbol description table 48. sw reset - software reset register (address b8h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 47 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. 10.2.3 hcbufferstatus register the hcbufferstatus register is used to indicate to the host controller that a particular ptd buffer (that is, atl, int, or iso) contains at least one ptd that must be scheduled. once the software sets the buffer filled bit of a particular transfer in the hcbufferstatus register, the host controller will start traversing through the ptd headers that are valid ptds and not marked for skipping. remark: the software can set these bits during the initialization. ta b l e 5 0 shows the bit allocation of the hcbufferstatus register. bit 7 6 5 4 3 2 1 0 symbol intf_mode[1:0] reserved [1] reset_atx reserved [1] reset_ hc reset_ all reset 00000 000 access r r r/w r/w r/w r/w r/w r/w table 49. sw reset - software reset register (address b8h) bit description bit symbol description 15 to 8 - reserved 7to6 intf_mode[1:0] interface mode : when read: 00b ? nand mode 01b ? generic mode 10b ? nor mode 11b ? sram mode writing to these bits have no effect. 5 to 4 - reserved 3 reset_atx reset atx : reset both transceivers. 0 ? no reset 1 ? enable reset remark: writing logic 1 followed by logic 0 will enable the software reset to atx. 2 - reserved 1 reset_hc reset host controller : reset only host controller-specific registers. 0 ? no reset 1 ? enable reset 0 reset_all reset all : reset all host controller and cpu interface registers. 0 ? no reset 1 ? enable reset table 50. hcbufferstatus - host controller buffer status register (address bah) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 48 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. 10.2.4 hcdmaconfiguration register the bit allocation of the hcdmaconfiguration register is given in ta b l e 5 2 . bit 7 6 5 4 3 2 1 0 symbol reserved [1] iso_buf_ fill int_buf_ fill atl_buf_ fill reset 00000 0 00 access r/w r/w r/w r/w r/w r/w r/w r/w table 51. hcbufferstatus - host controller buffer status register (address bah) bit description bit symbol description 15 to 3 - reserved 2 iso_buf_ fill iso buffer filled : 1 ? indicates one of the iso ptds is filled, and the iso ptd area will be processed. 0 ? indicates there is no ptd in this area. therefore, processing of iso ptds will be completely skipped. 1 int_buf_ fill int buffer filled : 1 ? indicates one of the int ptds is filled, and the int ptd area will be processed. 0 ? indicates there is no ptd in this area. therefore, processing of int ptds will be completely skipped. 0atl_buf_ fill atl buffer filled : 1 ? indicates one of the atl ptds is filled, and the atl ptd area will be processed. 0 ? indicates there is no ptd in this area. therefore, processing of atl ptds will be completely skipped. table 52. hcdmaconfiguration - host controller direct memory access configuration register (address bch) bit allocation bit 31 30 29 28 27 26 25 24 symbol dma_counter[23:16] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol dma_counter[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol dma_counter[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 49 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. 10.2.5 atl done timeout register the bit description of the atl done timeout register is given in table 54 . 10.2.6 memory register the memory register contains the base memory read or write address. this register must be set only before a first memory read cycle. once written, the address will be latched and will be incremented for every read until a new address is written to change the address pointer. bit 7 6 5 4 3 2 1 0 symbol dis_dma_ data port reserved [1] burst_len[1:0] enable_ dma dma_read _write_ sel reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 53. hcdmaconfiguration - host controller direct memory access configuration register (address bch) bit description bit symbol description 31 to 8 dma_counter [23:0] dma counter : the number of bytes to be transferred (read or write). remark: different number of bursts will be generated for the same transfer length programmed in 8-bit and 16-bit modes because dma_counter is in number of bytes. 7 dis_dma_data_ port disable dma data port : 0 ? enable dma data port. 1 ? disable dma data port. 6 to 4 - reserved 3 to 2 burst_len[1:0] dma burst length : 00 ? single dma burst 01 ? 4-cycle dma burst 10 ? 8-cycle dma burst 11 ? 16-cycle dma burst 1 enable_dma enable dma : 0 ? te r m i n a t e d m a 1 ? enable dma 0 dma_read_ write_sel dma read or write select : indicates if the dma operation is a write to or read from the isp1763a. 0 ? dma write to the isp1763a internal ram. 1 ? dma read from the isp1763a internal ram. table 54. atl done timeout register (address: c0h) bit description legend: * reset value bit symbol access value description 31 to 0 atl_done_ timeout [31:0] r/w 0000 0000h* atl done timeout : this register determines the atl done time-out interrupt. this register defines the time-out in seconds after which the isp1763a asserts the int line, if enabled. it is applicable to atl done ptds only.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 50 of 135 isp1763a hi-speed usb otg controller the bit description of the register is given in ta b le 5 5 . 10.2.7 data port register ta b l e 5 7 shows the bit description of this register. 10.2.8 edge interrupt count register ta b l e 5 8 shows the bit allocation of the register. [1] the reserved bits should always be written with the reset value. table 55. memory register (address c4h) bit allocation bit 15 14 13 12 11 10 9 8 symbol start_addr_mem[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol start_addr_mem[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 56. memory register (address c4h) bit description bit symbol description 15 to 0 start_addr_mem[15:0] start address for memory read or write cycles : the start address for a series of memory read or write cycles at incremental addresses in a contiguous space. table 57. data port register (address: c6h) bit description legend: * reset value bit symbol access value description 15 to 0 data_port[15:0] r/w 0000h* data port : this register is used to access the host controller memory. table 58. edge interrupt count register (address c8h) bit allocation bit 31 30 29 28 27 26 25 24 symbol min_width[7:0] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol reserved [1] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol no_of_clk[15:8] reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol no_of_clk[7:0] reset 00001111 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 51 of 135 isp1763a hi-speed usb otg controller 10.2.9 dma data port register ta b l e 6 0 for the bit description of the dma data port register. 10.2.10 dma start address register this register defines the start address select for the dma read and write operations. see ta b l e 6 1 for bit description. 10.2.11 power down control register this register is used to turn off power to internal blocks of the isp1763a to obtain maximum power savings. ta b le 6 2 shows the bit allocation of the register. table 59. edge interrupt count register (address c8h) bit description bit symbol description 31 to 24 min_width [7:0] minimum width : indicates the minimum width between two edge interrupts in sofs (1 sof = 125 s). this is not valid for level interrupts. a count of zero means that an interrupt occurs as and when an event occurs. 23 to 16 - reserved 15 to 0 no_of_ clk[15:0] number of clocks : number of clocks that the edge interrupt must be kept asserted on the interface. 15 clocks of 30 mhz on por if this register has a value of 000fh. the default int pulse width is approximately 500 ns. zero is an invalid setting for these bits. table 60. dma data port register (address 60h) bit description bit symbol access value description 15 to 0 dma_data_port[15:0] r/w - dma data port : access the memory through dma. table 61. dma start address register (address cch) bit description legend: * reset value bit symbol access value description 15 to 0 start_addr_ dma[15:0] w 0000h* start address for dma : the start address for dma read or write cycles. table 62. power down control register (address d0h) bit allocation bit 31 30 29 28 27 26 25 24 symbol clk_off_counter[15:8] reset 00 000011 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol clk_off_counter[7:0] reset 11 101000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol p2_ force_fs p1_ force_fs reserved [1] port2_ pd reserved [1] p2_oc_en p1_oc_en reset 0 0 011011 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 52 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. bit 7 6 5 4 3 2 1 0 symbol atx2_ pwron reserved [1] reg_pwr reg_ susp_ pwr reserved [1] p2_otg_ en p1_otg_ en hc_clk_ en reset 10 100000 access r/w r/w r/w r/w r/w r/w r/w r/w table 63. power down control register (address d0h) bit description bit symbol description 31 to 16 clk_off_ counter[15:0] clock off counter : determines the wake-up status duration after any wake-up event before the isp1763a goes back into suspend mode. this time-out is applicable only if, during the given interval, the host controller is not programmed back to the normal functionality. the setting of this register is based on the lazyclock frequency. 15 p2_force_fs port 2 force full-speed : 0 ? port 2 is not forced into full-speed. 1 ? force port 2 into full-speed. 14 p1_force_fs port 1 force full-speed : 0 ? port 1 is not forced into full-speed. 1 ? force port 1 into full-speed. 13 to 12 - reserved 11 port2_pd port 2 pull-down : controls port 2 pull-down resistors. 0 ? port 2 internal pull-down resistors are not connected. 1 ? port 2 internal pull-down resistors are connected. 10 - reserved 9p2_oc_en port 2 overcurrent enable : 0 ? disable overcurrent on port 2. 1 ? enable overcurrent on port 2. 8p1_oc_en port 1 overcurrent enable : 0 ? disable overcurrent on port 1. 1 ? enable overcurrent on port 1. 7 atx2_pwron atx2 power on : controls the atx2 suspend. 0 ? atx2 is suspended. atx2 macrocell is in suspend mode that draws minimal power from supplies. 1 ? atx2 is in normal operational mode. atx2 macrocell draws normal current. 6 - reserved 5reg_pwr regulator powered : controls the power-down mode. 0 ? the device is set to power-down mode. output of the regulator is shut down. the digital core has no power supply. the device can be woken up by a dummy read from the pio interface. 1 ? the regulator is in normal or suspend mode. 4 reg_susp_pwr regulator suspend circuit powered : controls regulator suspend. 0 ? the regulator is in normal or power-down mode. 1 ? the regulator is in suspend mode. the digital core can draw limited current from the regulator. 3 - reserved
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 53 of 135 isp1763a hi-speed usb otg controller 10.3 interrupt registers 10.3.1 hcinterrupt register the bits of this register indicate the interrupt source, defining the events that determined the int generation. clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position. all bits must be reset before enabling new interrupt events. these bits will be set, regardless of the setting of bit global_intr_en in the hw mode control register. table 64 shows the bit allocation of the hcinterrupt register. [1] the reserved bits should always be written with the reset value. 2 p2_otg_en port 2 otg comparators enable : controls the otg detection for port 2. 0 ? atx otg detection is powered off. 1 ? atx otg detection is powered on. port 2 works with host mode only. this bit helps to detect dp asserted (dp2_srp) and a-session valid for the a-device (a2_sess_vld). 1 p1_otg_en port 1 otg comparators enable : controls the otg detection for port 1. 0 ? atx otg detection is powered off. v bus detection is still on for device mode. 1 ? atx otg detection is powered on. in device mode, to reduce power consumption, the otg detection can be switched off. an independent circuit will assist port 1 to sense polarity changes on v bus . 0 hc_clk_en host controller clock enabled : controls internal clocks during suspend. 0 ? clocks are disabled during suspend. this is the default value. only the lazyclock of 100 khz will be left running in suspend if this bit is logic 0. if clocks are stopped during suspend, clkready int will be generated when all clocks are running stable. 1 ? all clocks are enabled even in suspend. table 63. power down control register (address d0h) bit description ?continued bit symbol description table 64. hcinterrupt - host controller interrupt register (address d4h) bit description bit 15 14 13 12 11 10 9 8 symbol reserved [1] otg_irq iso_irq atl_irq reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol int_irq clk ready hcsusp opr_reg dmaeot int reserved [1] sofint msofint reset 01000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 54 of 135 isp1763a hi-speed usb otg controller table 65. hcinterrupt - host controller interrupt register (address d4h) bit description bit symbol description 15 to 11 - reserved 10 otg_irq otg irq : indicates that an otg event occurred. the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no otg event. 1 ? otg event occurred. for details, see section 8.9.3 . 9iso_irq iso irq : indicates that an iso ptd was completed, or the ptds corresponding to the bits set in the iso irq mask and or iso irq mask or register bits combination were completed. the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no iso ptd event occurred. 1 ? iso ptd event occurred. for details, see section 8.9.3 . 8 atl_irq atl irq : indicates that an atl ptd was completed, or the ptds corresponding to the bits set in the atl irq mask and or atl irq mask or register bits combination were completed. the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no atl ptd event occurred. 1 ? atl ptd event occurred. for details, see section 8.9.3 . 7 int_irq int irq : indicates that an int ptd was completed, or the ptds corresponding to the bits set in the int irq mask and or int irq mask or register bits combination were completed. the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no int ptd event occurred. 1 ? int ptd event occurred. for details, see section 8.9.3 . 6 clkready clock ready : indicates that internal clock signals are running stable. the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no clkready event has occurred. 1 ? clkready event occurred. 5 hcsusp host controller suspend : indicates that the host controller has entered suspend mode. the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? the host controller did not enter suspend mode. 1 ? the host controller entered suspend mode. if the interrupt service routine (isr) accesses the isp1763a, it will wake up for the time specified in bits 31 to 16 of the power down control register.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 55 of 135 isp1763a hi-speed usb otg controller 10.3.2 hcinterruptenable register this register allows enabling or disabling of the int generation because of various events as described in table 66 . [1] the reserved bits should always be written with the reset value. 4 opr_reg operational registers : indicates an int was generated because of at least one change in operational registers. 0 ? no int because of operational registers change. 1 ? int generated because of at least one change in operational registers. 3dmaeot int dma eot interrupt : indicates the dma transfer completion. the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no dma transfer is completed. 1 ? dma transfer is completed. 2 - reserved; value is zero just after reset and changes to one after a short while 1sofint sof interrupt : the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no sof event has occurred. 1 ? sof event has occurred. 0msofint sof itl interrupt : the int line will be asserted if the respective enable bit in the hcinterruptenable register is set. 0 ? no sof event has occurred. 1 ? sof event has occurred. table 65. hcinterrupt - host controller interrupt register (address d4h) bit description ?continued bit symbol description table 66. hcinterruptenable - host controller interrupt enable register (address d6h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] otg_irq_ e iso_irq_ e atl_irq_ e reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol int_irq_e clk ready_e hcsusp_ e opr_reg _e dmaeot int_e reserved [1] sofint _e msofint _e reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 56 of 135 isp1763a hi-speed usb otg controller table 67. hcinterruptenable - host controller interrupt enable register (address d6h) bit description bit symbol description 15 to 11 - reserved 10 otg_irq_e otg irq enable : controls the int assertion because of events present in the otg interrupt latch register. 0 ? no int will be asserted. 1 ? int will be asserted. for details, see section 8.9.3 . 9 iso_irq_e iso irq enable : controls the int assertion when one or more iso ptds matching the iso irq mask and or iso irq mask or register bits combination are completed. 0 ? no int will be asserted when iso ptds are completed. 1 ? int will be asserted. for details, see section 8.9.3 . 8 atl_irq_e atl irq enable : controls the int assertion when one or more atl ptds matching the atl irq mask and or atl irq mask or register bits combination are completed. 0 ? no int will be asserted when atl ptds are completed. 1 ? int will be asserted. for details, see section 8.9.3 . 7 int_irq_e int irq enable : controls the int assertion when one or more int ptds matching the int irq mask and or int irq mask or register bits combination are completed. 0 ? no int will be asserted when int ptds are completed. 1 ? int will be asserted. for details, see section 8.9.3 . 6 clkready_e clock ready enable : enables the int assertion when internal clock signals are running stable. useful after wake-up. 0 ? no int will be generated after clkready_e event. 1 ? int will be generated after a clkready_e event. 5 hcsusp_e host controller suspend enable : enables the int generation when the host controller enters suspend mode. 0 ? no int will be generated when the host controller enters suspend mode. 1 ? int will be generated when the host controller enters suspend mode. 4 opr_reg_e operational registers enable : controls the int generation because of at least one change in operational registers. 0 ? no int will be generated on any change in operational registers. 1 ? int will be generated after a bit change, set by the software or hardware internally modified by the host controller, in the operational registers. 3 dmaeot int_e dma eot interrupt enable : controls assertion of int on the dma transfer completion. 0 ? no int will be generated when a dma transfer is completed. 1 ? int will be asserted when a dma transfer is completed. 2 - reserved 1sofint_e sof interrupt enable : controls the int generation at every sof occurrence. 0 ? no int will be generated on sof occurrence. 1 ? int will be asserted at every sof. 0msofint_e sof interrupt enable : controls the int generation at every sof occurrence. 0 ? no int will be generated on sof occurrence. 1 ? int will be asserted at every sof.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 57 of 135 isp1763a hi-speed usb otg controller 10.3.3 iso irq mask or register each bit of this register corresponds to one of the 16 iso ptds defined, and is a hardware int mask for each ptd done map. see ta b le 6 8 for the bit description. 10.3.4 int irq mask or register each bit of this register (see ta b le 6 9 ) corresponds to one of the 16 int ptds defined, and is a hardware int mask for each ptd done map. 10.3.5 atl irq mask or register each bit of this register corresponds to one of the 16 atl ptds defined, and is a hardware int mask for each ptd done map. see ta b le 7 0 for the bit description. 10.3.6 iso irq mask and register each bit of this register corresponds to one of the 16 iso ptds defined, and is a hardware int mask for each ptd done map. see ta b le 7 1 for the bit description. table 68. iso irq mask or register (address d8h) bit description legend: * reset value bit symbol access value description 15 to 0 iso_irq_ mask_or[15:0] r/w 0000h* iso irq mask or : represents a direct map for iso ptds 15 to 0. 0 ? no or condition defined between iso ptds 1 ? the bits corresponding to certain ptds are set to logic 1 to define a certain or condition table 69. int irq mask or register (address dah) bit description legend: * reset value bit symbol access value description 15 to 0 int_irq_ mask_ or[15:0] r/w 0000h* int irq mask or : represents a direct map for int ptds 15 to 0. 0 ? no or condition defined between int ptds 15 to 0. 1 ? the bits corresponding to certain ptds are set to logic 1 to define a certain or condition. table 70. atl irq mask or register (address dch) bit description legend: * reset value bit symbol access value description 15 to 0 atl_irq_ mask_or [15:0] r/w 0000h* atl irq mask or : represents a direct map for atl ptds 15 to 0. 0 ? no or condition defined between atl ptds. 1 ? the bits corresponding to certain ptds are set to logic 1 to define a certain or condition. table 71. iso irq mask and register (address deh) bit description legend: * reset value bit symbol access value description 15 to 0 iso_irq_ mask_and [15:0] r/w 0000h* iso irq mask and : represents a direct map for iso ptds 15 to 0. 0 ? no and condition defined between iso ptds. 1 ? the bits corresponding to certain ptds are set to logic 1 to define a certain and condition between 16 int ptds.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 58 of 135 isp1763a hi-speed usb otg controller 10.3.7 int irq mask and register each bit of this register (see ta b le 7 2 ) corresponds to one of the 16 int ptds defined, and is a hardware int mask for each ptd done map. 10.3.8 atl irq mask and register each bit of this register corresponds to one of the 16 atl ptds defined, and is a hardware int mask for each ptd done map. see ta b le 7 3 for the bit description. 10.4 proprietary transfer descriptor (ptd) the standard ehci data structures as described in enhanced host controller interface specification for universal serial bus rev. 1.0 are optimized for the bus master operation that is managed by the hardware state machine. the ptd structures of the isp1763a are translations of ehci data structures that are optimized for the isp1763a. they, however, still follow the basic ehci architecture. this optimized form of ehci data structures is necessary because the isp1763a is a slave host controller and has no bus master capability. ehci manages schedules in two lists: periodic and asynchronous. data structures are designed to provide the maximum flexibility required by usb, minimize memory traffic, and reduce hardware and software complexity. the isp1763a controller executes transactions for devices by using a simple shared-memory schedule. this schedule consists of data structures organized into three lists. qiso ? isochronous transfer qintl ? interrupt transfer qatl ? asynchronous transfer; for the control and bulk transfers the system software maintains two lists for the host controller: periodic and asynchronous. the isp1763a has a maximum of 16 iso, 16 intl, and 16 atl ptds. these ptds are used as channels to transfer data from the shared memory to the usb bus. these channels are allocated and deallocated on receiving the transfer from the core usb driver. table 72. int irq mask and register (address e0h) bit description legend: * reset value bit symbol access value description 15 to 0 int_irq_ mask_and [15:0] r/w 0000h* int irq mask and : represents a direct map for int ptds 15 to 0. 0 ? no or condition defined between int ptds. 1 ? the bits corresponding to certain ptds are set to logic 1 to define a certain and condition between 16 int ptds. table 73. atl irq mask and register (address e2h) bit description legend: * reset value bit symbol access value description 15 to 0 atl_irq_ mask_and [15:0] r/w 0000h* int irq mask and : represents a direct map for atl ptds 15 to 0. 0 ? no or condition defined between atl ptds. 1 ? the bits corresponding to certain ptds are set to logic 1 to define a certain and condition between 16 atl ptds.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 59 of 135 isp1763a hi-speed usb otg controller multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by endpoint data structures, until it reaches the end of the endpoint list. there are three endpoint lists: one for iso endpoints, and the other for intl and atl endpoints. if the schedule is enabled, the host controller executes the iso schedule, followed by the intl schedule, and then the atl schedule. these lists are traversed and scheduled by the software according to the ehci traversal rule. the host controller executes scheduled iso, intl, and atl ptds. the completion of a transfer is indicated to the software by the interrupt that can be grouped under various ptds by using the and or or registers that are available for each schedule type: iso, intl, and atl. these registers are simple logic registers to decide the completion status of group and individual ptds. when the logical conditions of the done bit are true in the shared memory, it means that ptd has completed. there are four types of interrupts in the isp1763a: iso, intl, atl, and sof. the latency can be programmed in multiples of sof (125 s).
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 60 of 135 isp1763a hi-speed usb otg controller 10.4.1 high-speed bulk in and out ta b l e 7 4 shows the bit allocation of the high-speed bulk in and out, asynchronous transfer descriptor. [1] reserved. [2] endpt[0]. table 74. high-speed bulk in and out: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved dw5 reserved dw3 ahbx [1] pdt cerr [1:0] nakcnt[3:0] reserved nrbytestransferred[14:0] (1 b to 20 kb for high-speed) dw1 reserved s eptype [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:0] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 reserved dw4 reserved dw2 reserved rl[3:0] [1] datastartaddress[15:0] reserved dw0 [2] mult [1:0] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 61 of 135 isp1763a hi-speed usb otg controller table 75. high-speed bulk in and out: bit description bit symbol access value description dw7 63 to 32 reserved - - - dw6 31 to 0 reserved - - - dw5 63 to 32 reserved - - - dw4 31 to 0 reserved - 0 not applicable for asynchronous td. dw3 63 a sw ? sets hw ? resets - active : write the same value as that in v. 62 h hw ? writes - halt : this bit corresponds to the halt bit of the status field of td. 61 b hw ? writes - babble : this bit corresponds to the babble detected bit in the status field of itd, sitd, or td. 1 ? when babbling is detected, a and v are set to 0. 60 x hw ? writes - error : this bit corresponds to the transaction error bit in the status field of itd, sitd, or td (exec_trans, the signal name is xacterr). 0 ? no pid error. 1 ? if there are pid errors, this bit is set to active. the a and v bits are also set to inactive. this transaction is retried three times. sw ? writes - 0 ? before scheduling. 59 reserved - - - 58 p sw ? writes hw ? updates - ping : for high-speed transactions, this bit corresponds to the ping state bit in the status field of a td. 0 ? ping is not set. 1 ? ping is set. for the first time, the software sets the ping bit to 0. for the successive asynchronous td, the software sets the bit in asynchronous td based on the state of the bit for the previous asynchronous td of the same transfer, that is: ? the current asynchronous td is completed with the ping bit set. ? the next asynchronous td will have its ping bit set by the software. 57 dt hw ? updates sw ? writes - data toggle : this bit is filled by the software to start a ptd. if nrbytestotransfer[14:0] is not complete, the software needs to read this value and then write back the same value to continue. 56 to 55 cerr[1:0] hw ? writes sw ? writes - error counter : this field corresponds to the cerr[1:0] field in td. the default value of this field is zero for isochronous transactions. 00 ? the transaction will not retry. 11 ? the transaction will retry three times. the hardware will decrement these values.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 62 of 135 isp1763a hi-speed usb otg controller 54 to 51 nakcnt[3:0] hw ? writes sw ? writes - nak counter : this field corresponds to the nakcnt field in td. the software writes for the initial ptd launch. the v bit is reset if nakcnt decrements to zero and rl is a non-zero value. it reloads from rl if transaction is ack-ed. 50 to 47 reserved - - - 46 to 32 nrbytes transferred [14:0] hw ? writes sw ? writes 0000 - number of bytes transferred : this field indicates the number of bytes sent or received for this transaction. if mult[1:0] is greater than one, it is possible to store intermediate results in this field. dw2 31 to 29 reserved - - set to 0 for asynchronous td. 28 to 25 rl[3:0] sw ? writes - reload : if rl[3:0] is set to 0h, the hardware ignores the nakcnt[3:0] value. rl[3:0] and nakcnt[3:0] are set to the same value before a transaction. 24 reserved - - always 0 for asynchronous td. 23 to 8 datastart address[15:0] sw ? writes - data start address : this is the start address for data that will be sent on or received from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address ? 400h) / 8 7to0 reserved - - - dw1 63 to 47 reserved - - always 0 for asynchronous td. 46 s sw ? writes - split : this bit indicates whether a split transaction has to be executed: 0 ? high-speed transaction 1 ? split transaction 45 to 44 eptype[1:0] sw ? writes - transaction type : 00 ? control 10 ? bulk 43 to 42 token[1:0] sw ? writes - token : identifies the token packet identifier (pid) for this transaction: 00 ? out 01 ? in 10 ? setup 11 ? ping (written by the hardware only) 41 to 35 deviceaddress [6:0] sw ? writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw ? writes - endpoint : this is the usb address of the endpoint within the function. dw0 31 endpt[0] sw ? writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 mult[1:0] sw ? writes - multiplier : this field is a multiplier used by the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. set this field to 01b. you can also set it to 11b and 10b depending on your application. 00b is undefined. table 75. high-speed bulk in and out: bit description ?continued bit symbol access value description
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 63 of 135 isp1763a hi-speed usb otg controller 28 to 18 maxpacket length[10:0] sw ? writes - maximum packet length : this field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. the maximum packet size for a bulk transfer is 512 bytes. the maximum packet size for the isochronous transfer is also variable at any whole number. 17 to 3 nrbytesto transfer[14:0] sw ? writes - number of bytes to transfer : this field indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data field (1 b to 20 kb). 2to1 reserved - - - 0v sw ? sets hw ? resets - valid : 0 ? this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 ? the software updates to one when there is payload to be sent or received. the current ptd is active. table 75. high-speed bulk in and out: bit description ?continued bit symbol access value description
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 64 of 135 isp1763a hi-speed usb otg controller 10.4.2 high-speed isochronous in and out ta b l e 7 6 shows the bit allocation of the high-speed isochronous in and out, isochronous transfer descriptor (itd). [1] reserved. [2] endpt[0]. table 76. high-speed isochronous in and out: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 isoin_7[11:0] isoin_6[11:0] isoin_5[11:4] dw5 isoin_2[7:0] isoin_1[11:0] isoin_0[11:0] dw3 a h b reserved nrbytestransferred[14:0] (1 b to 20 kb for high-speed) dw1 reserved s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:0] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 isoin_5[3:0] isoin_4[11:0] isoin_3[11:0] isoin_2[11:8] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] sa[7:0] dw2 reserved datastartaddress[15:0] frame[7:0] dw0 [2] mult [1:0] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 65 of 135 isp1763a hi-speed usb otg controller table 77. high-speed isochronous in and out: bit description bit symbol access value description dw7 63 to 52 isoin_7[11:0] hw ? writes - isochronous in 7 : bytes received during sof7, if sa[7] is set to 1 and frame number is correct. 51 to 40 isoin_6[11:0] hw ? writes - isochronous in 6 : bytes received during sof6, if sa[6] is set to 1 and frame number is correct. 39 to 32 isoin_5[11:4] hw ? writes - isochronous in 5 : bytes received during sof5 (bits 11 to 4), if sa[5] is set to 1 and frame number is correct. dw6 31 to 28 isoin_5[3:0] hw ? writes - isochronous in 5 : bytes received during sof5 (bits 3 to 0), if sa[5] is set to 1 and frame number is correct. 27 to 16 isoin_4[11:0] hw ? writes - isochronous in 4 : bytes received during sof4, if sa[4] is set to 1 and frame number is correct. 15 to 4 isoin_3[11:0] hw ? writes - isochronous in 3 : bytes received during sof3, if sa[3] is set to 1 and frame number is correct. 3to0 isoin_2[11:8] hw ? writes - isochronous in 2 : bytes received during sof2 (bits 11 to 8), if sa[2] is set to 1 and frame number is correct. dw5 63 to 56 isoin_2[7:0] hw ? writes - isochronous in 2 : bytes received during sof2 (bits 7 to 0), if sa[2] is set to 1 and frame number is correct. 55 to 44 isoin_1[11:0] hw ? writes - isochronous in 1 : bytes received during sof1, if sa[1] is set to 1 and frame number is correct. 43 to 32 isoin_0[11:0] hw ? writes - isochronous in 0 : bytes received during sof0, if sa[0] is set to 1 and frame number is correct. dw4 31 to 29 status7[2:0] hw ? writes - status 7 : iso in or out status at sof7 28 to 26 status6[2:0] hw ? writes - status 6 : iso in or out status at sof6 25 to 23 status5[2:0] hw ? writes - status 5 : iso in or out status at sof5 22 to 20 status4[2:0] hw ? writes - status 4 : iso in or out status at sof4 19 to 17 status3[2:0] hw ? writes - status 3 : iso in or out status at sof3 16 to 14 status2[2:0] hw ? writes - status 2 : iso in or out status at sof2 13 to 11 status1[2:0] hw ? writes - status 1 : iso in or out status at sof1 10 to 8 status0[2:0] hw ? writes - status 0 : status of the payload on the usb bus for this sof after iso has been delivered. bit 0 ? transaction error (in and out) bit 1 ? babble (in token only) bit 2 ? underrun (out token only) 7to0 sa[7:0] sw ? writes (0 1) hw ? writes (1 0) after processing - sof active : when the frame number of bits dw2[7:3] match the frame number of the usb bus, these bits are checked for 1 before they are sent for sof. for example: if sa[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send iso every sof of the entire millisecond. if sa[7:0] = 0, 1, 0, 1, 0, 1, 0, 1: send iso only on sof0, sof2, sof4, and sof6. dw3 63 a sw ? sets - active : this bit is the same as the valid bit.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 66 of 135 isp1763a hi-speed usb otg controller 62 h hw ? writes - halt : only one bit for the entire millisecond. when this bit is set, the valid bit is reset. the device decides to stall an endpoint. 61 b hw ? writes - babble : not applicable here. 60 to 47 reserved - 0 set to 0 for isochronous. 46 to 32 nrbytes transferred [14:0] hw ? writes - number of bytes transferred : this field indicates the number of bytes sent or received for this transaction. if mult[1:0] is greater than one, it is possible to store intermediate results in this field. nrbytestransferred[14:0] is 1 b to 20 kb per ptd. dw2 31 to 24 reserved - 0 set to 0 for isochronous. 23 to 8 datastart address[15:0] sw ? writes - data start address : this is the start address for data that will be sent on or received from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address ? 400h) / 8 7to0 frame[7:0] sw ? writes - frame : bits 2 to 0 ? don?t care bits 7 to 3 ? frame number that this ptd will be sent for iso out or in dw1 63 to 47 reserved - - - 46 s sw ? writes - split : this bit indicates whether a split transaction must be executed. 0 ? high-speed transaction 1 ? split transaction 45 to 44 eptype[1:0] sw ? writes - endpoint type : 01 ? isochronous 43 to 42 token[1:0] sw ? writes - token : this field indicates the token pid for this transaction: 00 ? out 01 ? in 41 to 35 device address[6:0] sw ? writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw ? writes - endpoint : this is the usb address of the endpoint within the function. dw0 31 endpt[0] sw ? writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 mult[1:0] sw ? writes - multiplier : this field is a multiplier counter used by the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. for details, refer to appendix d of enhanced host controller interface specification for universal serial bus rev. 1.0 . 28 to 18 maxpacket length[10:0] sw ? writes - maximum packet length : this field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. the maximum packet size for an isochronous transfer is 1024 bytes. the maximum packet size for the isochronous transfer is also variable at any whole number. table 77. high-speed isochronous in and out: bit description ?continued bit symbol access value description
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 67 of 135 isp1763a hi-speed usb otg controller 17 to 3 nrbytesto transfer[14:0] sw ? writes - number of bytes to transfer : this field indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data field (1 b to 20 kb). 2to1 reserved - - - 0v hw ? resets sw ? sets - valid : 0 ? this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 ? the software updates to one when there is payload to be sent or received. the current ptd is active. table 77. high-speed isochronous in and out: bit description ?continued bit symbol access value description
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 68 of 135 isp1763a hi-speed usb otg controller 10.4.3 high-speed interrupt in and out ta b l e 7 8 shows the bit allocation of the high-speed interrupt in and out, periodic transfer descriptor (ptd). [1] reserved. [2] endpt[0]. table 78. high-speed interrupt in and out: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 int_in_7[11:0] int_in_6 [11:0] int_in_5[11:4] dw5 int_in_2[7:0] int_in_1[11:0] int_in_0[11:0] dw3 a h reserved dt cerr [1:0] reserved nrbytestransferred[14:0] (1 b to 20 kb for high-speed) dw1 reserved s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:0] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 int_in_5[3:0] int_in_4[11:0] int_in_3[11:0] int_in_2[11:8] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] sa[7:0] dw2 reserved datastartaddress[15:0] frame[7:0] dw0 [2] mult [1:0] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 69 of 135 isp1763a hi-speed usb otg controller table 79. high-speed interrupt in and out: bit description bit symbol access value description dw7 63 to 52 int_in_7[11:0] hw ? writes - interrupt in 7 : bytes received during sof7, if sa[7] is set to 1 and frame number is correct. 51 to 40 int_in_6[11:0] hw ? writes - interrupt in 6 : bytes received during sof6, if sa[6] is set to 1 and frame number is correct. 39 to 32 int_in_5[11:4] hw ? writes - interrupt in 5 : bytes received during sof5 (bits 11 to 4), if sa[5] is set to 1 and frame number is correct. dw6 31 to 28 int_in_5[3:0] hw ? writes - interrupt in 5 : bytes received during sof5 (bits 3 to 0), if sa[5] is set to 1 and frame number is correct. 27 to 16 int_in_4[11:0] hw ? writes - interrupt in 4 : bytes received during sof4, if sa[4] is set to 1 and frame number is correct. 15 to 4 int_in_3[11:0] hw ? writes - interrupt in 3 : bytes received during sof3, if sa[3] is set to 1 and frame number is correct. 3 to 0 int_in_2[11:8] hw ? writes - interrupt in 2 : bytes received during sof2 (bits 11 to 8), if sa[2] is set to 1 and frame number is correct. dw5 63 to 56 int_in_2[7:0] hw ? writes - interrupt in 2 : bytes received during sof2 (bits 7 to 0), if sa[2] is set to 1 and frame number is correct. 55 to 44 int_in_1[11:0] hw ? writes - interrupt in 1 : bytes received during sof1, if sa[1] is set to 1 and frame number is correct. 43 to 32 int_in_0[11:0] hw ? writes - interrupt in 0 : bytes received during sof0, if sa[0] is set to 1 and frame number is correct. dw4 31 to 29 status7[2:0] hw ? writes - status 7 : int in or out status of sof7 28 to 26 status6[2:0] hw ? writes - status 6 : int in or out status of sof6 25 to 23 status5[2:0] hw ? writes - status 5 : int in or out status of sof5 22 to 20 status4[2:0] hw ? writes - status 4 : int in or out status of sof4 19 to 17 status3[2:0] hw ? writes - status 3 : int in or out status of sof3 16 to 14 status2[2:0] hw ? writes - status 2 : int in or out status of sof2 13 to 11 status1[2:0] hw ? writes - status 1 : int in or out status of sof1 10 to 8 status0[2:0] hw ? writes - status 0 : status of the payload on the usb bus for this sof after int has been delivered. bit 0 ? transaction error (in and out) bit 1 ? babble (in token only) bit 2 ? underrun (out token only) 7to0 sa[7:0] sw ? writes (0 1) hw ? writes (1 0) after processing - sa[7:0] : when the frame number of bits dw2[7:3] match the frame number of the usb bus, these bits are checked for 1 before they are sent for sof. for example: when sa[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send int for every sof of the entire millisecond. when sa[7:0] = 0, 1, 0, 1, 0, 1, 0, 1: send int for sof0, sof2, sof4, and sof6. when sa[7:0] = 1, 0, 0, 0, 1, 0, 0, 0: send int for every fourth sof.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 70 of 135 isp1763a hi-speed usb otg controller dw3 63 a hw ? writes sw ? writes - active : write the same value as that in v. 62 h hw ? writes - halt : transaction is halted. 61 to 58 reserved - - - 57 dt hw ? writes sw ? writes - data toggle : set the data toggle bit to start the ptd. the software writes the current transaction toggle value. the hardware writes the next transaction toggle value. 56 to 55 cerr[1:0] hw ? writes sw ? writes - error counter : this field corresponds to the cerr[1:0] field in td. the default value of this field is zero for isochronous transactions. 54 to 47 reserved - - - 46 to 32 nrbytes transferred [14:0] hw ? writes - number of bytes transferred : this field indicates the number of bytes sent or received for this transaction. if mult[1:0] is greater than one, it is possible to store intermediate results in this field. dw2 31 to 24 reserved - - - 23 to 8 datastart address[15:0] sw ? writes - data start address : this is the start address for data that will be sent on or received from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address ? 400h) / 8 7to0 frame[7:0] sw ? writes - frame : bits 7 to 3 represent the polling rate in milliseconds. the int polling rate is defined as 2 (b ? 1) sof, where b is 1 to 9. when b is 1, 2, 3, or 4, use sa to define polling because the rate is equal to or less than 1 ms. bits 7 to 3 are set to 0. polling checks sa bits for sof rates. see ta bl e 8 0 . dw1 63 to 47 reserved - - - 46 s sw ? writes - split : this bit indicates if a split transaction has to be executed: 0 ? high-speed transaction 1 ? split transaction 45 to 44 eptype[1:0] sw ? writes - endpoint type : 11 ? interrupt 43 to 42 token[1:0] sw ? writes - token : this field indicates the token pid for this transaction: 00 ? out 01 ? in 41 to 35 deviceaddress [6:0] sw ? writes - device address : this is the usb address of the function containing the endpoint that is referred to by the buffer. 34 to 32 endpt[3:1] sw ? writes - endpoint : this is the usb address of the endpoint within the function. dw0 31 endpt[0] sw ? writes - endpoint : this is the usb address of the endpoint within the function. table 79. high-speed interrupt in and out: bit description ?continued bit symbol access value description
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 71 of 135 isp1763a hi-speed usb otg controller 30 to 29 mult[1:0] sw ? writes - multiplier : this field is a multiplier counter used by the host controller as the number of successive packets the host controller may submit to the endpoint in the current execution. set this field to 01b. you can also set it to 11b and 10b depending on your application. 00b is undefined. 28 to 18 maxpacket length[10:0] sw ? writes - maximum packet length : this field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. 17 to 3 nrbytesto transfer[14:0] sw ? writes - number of bytes to transfer : this field indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data field (1 b to 20 kb). 2to1 reserved - - - 0v sw ? sets hw ? resets - valid : 0 ? this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 ? the software updates to one when there is payload to be sent or received. the current ptd is active. table 79. high-speed interrupt in and out: bit description ?continued bit symbol access value description table 80. microframe description b rate frame[7:3] sa[7:0] 11 sof 0 0000 1111 1111 22 sof 0 0000 1010 1010 or 0101 0101 34 sof 0 0000 any 2 bits set 4 1 ms 0 0000 any 1 bit set 5 2 ms 0 0001 any 1 bit set 6 4 ms 0 0010 to 0 0011 any 1 bit set 7 8 ms 0 0100 to 0 0111 any 1 bit set 8 16 ms 0 1000 to 0 1111 any 1 bit set 9 32 ms 1 0000 to 1 1111 any 1 bit set
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 72 of 135 isp1763a hi-speed usb otg controller 10.4.4 start and complete split for bulk ta b l e 8 1 shows the bit allocation of start split (ss) and complete split (cs) for bulk, asynchronous start split, and complete split (ss/cs) transfer descriptor. [1] reserved. [2] endpt[0]. table 81. start and complete split for bulk: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved dw5 reserved dw3 ahbxsc [1] dt cerr [1:0] nakcnt[3:0] reserved nrbytestransferred[14:0] dw1 hubaddress[6:0] portnumber[6:0] se[1:0] re tire sep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:0] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 reserved dw4 reserved dw2 reserved rl[3:0] [1] datastartaddress[15:0] reserved dw0 [2] [1] maxpacketlength[10:0] nrbytestotransfer[14:0] [1] v
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 73 of 135 isp1763a hi-speed usb otg controller table 82. start and complete split for bulk: bit description bit symbol access value description dw7 63 to 32 reserved - - - dw6 31 to 0 reserved - - - dw5 63 to 32 reserved - - - dw4 31 to 0 reserved - - - dw3 63 a sw ? sets hw ? resets - active : write the same value as that in v. 62 h hw ? writes - halt : this bit corresponds to the halt bit of the status field of td. 61 b hw ? writes - babble : this bit corresponds to the babble detected bit in the status field of itd, sitd, or td. 1 ? when babbling is detected, a and v are set to 0. 60 x hw ? writes - transaction error : this bit corresponds to the transaction error bit in the status field. sw ? writes - 0 ? before scheduling 59 sc sw ? writes 0 hw ? updates - start/complete : 0 ? start split 1 ? complete split 58 reserved - - - 57 dt hw ? writes sw ? writes - data toggle : set the data toggle bit to start for the ptd. 56 to 55 cerr[1:0] hw ? updates sw ? writes - error counter : this field contains the error count for asynchronous start and complete split (ss/cs) td. when an error has no response or bad response, cerr[1:0] will be decremented to zero and then valid will be set to zero. a nak or nyet will reset cerr[1:0]. for details, refer to section 4.12.1.2 of enhanced host controller interface specification for universal serial bus rev. 1.0 . if retry has insufficient time at the beginning of a new sof, the first ptd must be this retry. this can be accomplished if aperiodic ptd is not advanced. 54 to 51 nakcnt[3:0] hw ? writes sw ? writes - nak counter : the v bit is reset if nakcnt decrements to zero and rl is a non-zero value. not applicable to isochronous split transactions. 50 to 47 reserved - - - 46 to 32 nrbytes transferred[14:0] hw ? writes - number of bytes transferred : this field indicates the number of bytes sent or received for this transaction. dw2 31 to 29 reserved - - -
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 74 of 135 isp1763a hi-speed usb otg controller 28 to 25 rl[3:0] sw ? writes - reload : if rl is set to 0h, the hardware ignores the nakcnt value. set rl and nakcnt to the same value before a transaction. for full-speed and low-speed transactions, set this field to 0000b. not applicable to isochronous start split and complete split. 23 to 8 datastart address[15:0] sw ? writes - data start address : this is the start address for data that will be sent on or received from the usb bus. this is the internal memory address and not the direct cpu address. ram address = (cpu address ? 400h) / 8 7to0 reserved - - - dw1 63 to 57 hubaddress[6:0] sw ? writes - hub address : this indicates the hub address. 56 to 50 portnumber[6:0] sw ? writes - port number : this indicates the port number of the hub or embedded tt. 49 to 48 se[1:0] sw ? writes - this depends on the endpoint type and direction. it is valid only for split transactions. table 83 applies to start split and complete split only. 47 retire sw ? writes - retire : set to 1 to abort this ptd. 46 s sw ? writes - split : this bit indicates whether a split transaction has to be executed: 0 ? high-speed transaction 1 ? split transaction 45 to 44 eptype[1:0] sw ? writes - endpoint type : 00 ? control 10 ? bulk 43 to 42 token[1:0] sw ? writes - token : this field indicates the pid for this transaction. 00 ? out 01 ? in 10 ? setup 41 to 35 deviceaddress[6:0] sw ? writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw ? writes - endpoint : this is the usb address of the endpoint within the function. dw0 31 endpt[0] sw ? writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 reserved - - - 28 to 18 maximumpacket length[10:0] sw ? writes - maximum packet length : this field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. the maximum packet size for full-speed is 64 bytes as defined in universal serial bus specification rev. 2.0 . table 82. start and complete split for bulk: bit description ?continued bit symbol access value description
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 75 of 135 isp1763a hi-speed usb otg controller 17 to 3 nrbytesto transfer[14:0] sw ? writes - number of bytes to transfer : this field indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data field. 2to1 reserved - - - 0v sw ? sets hw ? resets - valid : 0 ? this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 ? the software updates to one when there is payload to be sent or received. the current ptd is active. table 82. start and complete split for bulk: bit description ?continued bit symbol access value description table 83. se description bulk control se1 se[0] remark i/o i/o 1 0 low-speed i/o i/o 0 0 full-speed
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 76 of 135 isp1763a hi-speed usb otg controller 10.4.5 start and complete split for isochronous ta b l e 8 4 shows the bit allocation for start and complete split for isochronous, split isochronous transfer descriptor (sitd). [1] reserved. [2] endpt[0]. table 84. start and complete split for isochronous: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved iso_in_7[7:0] dw5 iso_in_2[7:0] iso_in_1[7:0] iso_in_0[7:0] scs[7:0] dw3 ahbxsc [1] dt reserved nrbytestransferred[11:0] dw1 hubaddress[6:0] portnumber[6:0] reserved s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:0] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 iso_in_6[7:0] iso_in_5[7:0] iso_in_4[7:0] iso_in_3[7:0] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] sa[7:0] dw2 reserved datastartaddress[15:0] frame[7:0] (full-speed) dw0 [2] [1] tt_mps_len[10:0] nrbytestotransfer[14:0] (1 kb for full-speed) [1] v
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 77 of 135 isp1763a hi-speed usb otg controller table 85. start and complete split for isochronous: bit description bit symbol access value description dw7 63 to 40 reserved - - - 39 to 32 iso_in_7[7:0] hw ? writes - isochronous in 7 : bytes received during sof7, if sa[7] is set to 1 and frame number is correct. dw6 31 to 24 iso_in_6[7:0] hw ? writes - isochronous in 6 : bytes received during sof6, if sa[6] is set to 1 and frame number is correct. 23 to 16 iso_in_5[7:0] hw ? writes - isochronous in 5 : bytes received during sof5, if sa[5] is set to 1 and frame number is correct. 15 to 8 iso_in_4[7:0] hw ? writes - isochronous in 4 : bytes received during sof4, if sa[4] is set to 1 and frame number is correct. 7 to 0 iso_in_3[7:0] hw ? writes - isochronous in 3 : bytes received during sof3, if sa[3] is set to 1 and frame number is correct. dw5 63 to 56 iso_in_2[7:0] hw ? writes - isochronous in 2 : bytes received during sof2, if sa[2] is set to 1 and frame number is correct. 55 to 48 iso_in_1[7:0] hw ? writes - isochronous in 1 : bytes received during sof1, if sa[1] is set to 1 and frame number is correct. 47 to 40 iso_in_0[7:0] hw ? writes - isochronous in 0 : bytes received during sof0 if sa[0] is set to 1 and frame number is correct. 39 to 32 scs[7:0] sw ? writes (0 1) hw ? writes (1 0) after processing - scs : all bits can be set to one for every transfer. it specifies which sof the complete split needs to be sent. valid only for in. start split and complete split active bits, sa = 0000 0001 and scs = 0000 0100, will cause ss to execute in frame0 and cs in frame2. dw4 31 to 29 status7[2:0] hw ? writes - status 7 : isochronous in or out status of sof7 28 to 26 status6[2:0] hw ? writes - status 6 : isochronous in or out status of sof6 25 to 23 status5[2:0] hw ? writes - status 5 : isochronous in or out status of sof5 22 to 20 status4[2:0] hw ? writes - status 4 : isochronous in or out status of sof4 19 to 17 status3[2:0] hw ? writes - status 3 : isochronous in or out status of sof3 16 to 14 status2[2:0] hw ? writes - status 2 : isochronous in or out status of sof2 13 to 11 status1[2:0] hw ? writes - status 1 : isochronous in or out status of sof1 10 to 8 status0[2:0] hw ? writes - status 0 : isochronous in or out status of sof0 bit 0 ? transaction error (in and out) bit 1 ? babble (in token only) bit 2 ? underrun (out token only) 7to0 sa[7:0] sw ? writes (0 1) hw ? writes (1 0) after processing - sa : specifies which sof the start split needs to be placed. for out token : when the frame number of bits dw2[7:3] matches the frame number of the usb bus, these bits are checked for one before they are sent for the sof. for in token : only sof0, sof1, sof2, or sof3 can be set to 1. nothing can be set for sof4 and above.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 78 of 135 isp1763a hi-speed usb otg controller dw3 63 a sw ? sets hw ? resets - active : write the same value as that in v. 62 h hw ? writes - halt : the halt bit is set when any microframe transfer status has a stalled or halted condition. 61 b hw ? writes - babble : this bit corresponds to bit 1 of status0 to status7 for every microframe transfer status. 60 x hw ? writes - transaction error : this bit corresponds to bit 0 of status0 to status7 for every microframe transfer status. 59 sc sw ? writes 0 hw ? updates - start/complete : 0 ? start split 1 ? complete split 58 reserved - - - 57 dt hw ? writes sw ? writes - data toggle : set the data toggle bit to start for the ptd. 56 to 44 reserved - - - 43 to 32 nrbytes transferred [11:0] hw ? writes - number of bytes transferred : this field indicates the number of bytes sent or received for this transaction. dw2 31 to 24 reserved - - - 23 to 8 datastart address[15:0] sw ? writes - data start address : this is the start address for data that will be sent on or received from the usb bus. this is the internal memory address and not the cpu address. 7to0 frame[7:0] sw ? writes - frame : bits 7 to 3 determine which frame to execute. dw1 63 to 57 hubaddress [6:0] sw ? writes - hub address : this indicates the hub address. 56 to 50 portnumber [6:0] sw ? writes - port number : this indicates the port number of the hub or embedded tt. 49 to 47 reserved - - - 46 s sw ? writes - split : this bit indicates whether a split transaction must be executed: 0 ? high-speed transaction 1 ? split transaction 45 to 44 eptype[1:0] sw ? writes - transaction type : 01 ? isochronous 43 to 42 token[1:0] sw ? writes - token : token pid for this transaction: 00 ? out 01 ? in 41 to 35 device address[6:0] sw ? writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw ? writes - endpoint : this is the usb address of the endpoint within the function. table 85. start and complete split for isochronous: bit description ?continued bit symbol access value description
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 79 of 135 isp1763a hi-speed usb otg controller dw0 31 endpt[0] sw ? writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 reserved - - - 28 to 18 tt_mps_len [10:0] sw ? writes - transaction translator maximum packet size length : this field indicates the maximum number of bytes that can be sent per start split depending on the number of total bytes needed. if the total bytes to be sent for the entire millisecond is greater than 188 bytes, this field must be set to 188 bytes for an out token and 192 bytes for an in token. otherwise, this field must be equal to the total bytes sent. 17 to 3 nrbytesto transfer[14:0] sw ? writes - number of bytes to transfer : this field indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data field. this field is restricted to 1023 bytes because in sitd the maximum allowable payload for a full-speed device is 1023 bytes. this field indirectly becomes the maximum packet size of the downstream device. 2to1 reserved - - - 0v sw ? sets hw ? resets - valid : 0 ? this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 ? the software updates to one when there is payload to be sent or received. the current ptd is active. table 85. start and complete split for isochronous: bit description ?continued bit symbol access value description
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 80 of 135 isp1763a hi-speed usb otg controller 10.4.6 start and complete split for interrupt ta b l e 8 6 shows the bit allocation of start and complete split for interrupt. [1] reserved. [2] endpt[0]. table 86. start and complete split for interrupt: bit allocation bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 dw7 reserved int_in_7[7:0] dw5 int_in_2[7:0] int_in_1[7:0] int_in_0[7:0] scs[7:0] dw3 ahbxsc [1] dt cerr [1:0] reserved nrbytestransferred[11:0] (4 kb for full-speed and low-speed) dw1 hubaddress[6:0]` portnumber[6:0] se[1:0] - s ep type [1:0] to k e n [1:0] deviceaddress[6:0] endpt[3:0] bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dw6 int_in_6[7:0] int_in_5[7:0] int_in_4[7:0] int_in_3[7:0] dw4 status7[2:0] status6[2:0] status5[2:0] status4[2:0] status3[2:0] status2[2:0] status1[2:0] status0[2:0] sa[7:0] dw2 reserved datastartaddress[15:0] frame[7:0] (full-speed and low-speed) dw0 [2] [1] maxpacketlength[10:0] nrbytestotransfer[14:0] (4 kb for full-speed and low-speed) [1] v
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 81 of 135 isp1763a hi-speed usb otg controller table 87. start and complete split for interrupt: bit description bit symbol access value description dw7 63 to 40 reserved - - - 39 to 32 int_in_7[7:0] hw ? writes - interrupt in 7 : bytes received during sof7, if sa[7] is set to 1 and frame number is correct. the new value continuously overwrites the old value. dw6 31 to 24 int_in_6[7:0] hw ? writes - interrupt in 6 : bytes received during sof6, if sa[6] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 23 to 16 int_in_5[7:0] hw ? writes - interrupt in 5 : bytes received during sof5, if sa[5] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 15 to 8 int_in_4[7:0] hw ? writes - interrupt in 4 : bytes received during sof4, if sa[4] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 7 to 0 int_in_3[7:0] hw ? writes - interrupt in 3 : bytes received during sof3, if sa[3] is set to 1 and frame number is correct. the new value continuously overwrites the old value. dw5 63 to 56 int_in_2[7:0] hw ? writes - interrupt in 2 : bytes received during sof2, if sa[2] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 55 to 48 int_in_1[7:0] hw ? writes - interrupt in 1 : bytes received during sof1, if sa[1] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 47 to 40 int_in_0[7:0] hw ? writes - interrupt in 0 : bytes received during sof0, if sa[0] is set to 1 and frame number is correct. the new value continuously overwrites the old value. 39 to 32 scs[7:0] sw ? writes (0 1) hw ? writes (1 0) after processing - scs : all bits can be set to one for every transfer. it specifies which sof the complete split needs to be sent. valid only for in. start split and complete split active bits, sa = 0000 0001 and scs = 0000 0100, will cause ss to execute in frame0 and cs in frame2. dw4 31 to 29 status7[2:0] hw ? writes - status 7 : interrupt in or out status of sof7 28 to 26 status6[2:0] hw ? writes - status 6 : interrupt in or out status of sof6 25 to 23 status5[2:0] hw ? writes - status 5 : interrupt in or out status of sof5 22 to 20 status4[2:0] hw ? writes - status 4 : interrupt in or out status of sof4 19 to 17 status3[2:0] hw ? writes - status 3 : interrupt in or out status of sof3 16 to 14 status2[2:0] hw ? writes - status 2 : interrupt in or out status of sof2 13 to 11 status1[2:0] hw ? writes - status 1 : interrupt in or out status of sof1 10 to 8 status0[2:0] hw ? writes - status 0 : interrupt in or out status of sof0 bit 0 ? transaction error (in and out) bit 1 ? babble (in token only) bit 2 ? underrun (out token only)
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 82 of 135 isp1763a hi-speed usb otg controller 7to0 sa[7:0] sw ? writes (0 1) hw ? writes (1 0) after processing - sa : specifies which sof the start split needs to be placed. for out token : when the frame number of bits dw2[7:3] matches the frame number of the usb bus, these bits are checked for one before they are sent for sof. for in token : only sof0, sof1, sof2, or sof3 can be set to 1. nothing can be set for sof4 and above. dw3 63 a sw ? sets hw ? resets - active : write the same value as that in v. 62 h hw ? writes - halt : the halt bit is set when any microframe transfer status has a stalled or halted condition. 61 b hw ? writes - babble : this bit corresponds to bit 1 of status0 to status7 for every microframe transfer status. 60 x hw ? writes - transaction error : this bit corresponds to bit 0 of status0 to status7 for every microframe transfer status. 59 sc sw ? writes 0 hw ? updates - start/complete : 0 ? start split 1 ? complete split 58 reserved - - - 57 dt hw ? writes sw ? writes - data toggle : for an interrupt transfer, set correct bit to start the ptd. 56 to 55 cerr[1:0] hw ? writes sw ? writes - error counter : this field corresponds to the cerr[1:0] field in td. 00 ? the transaction will not retry. 11 ? the transaction will retry three times. the hardware will decrement these values. 54 to 44 reserved - - - 43 to 32 nrbytes transferred[11:0] hw ? writes - number of bytes transferred : this field indicates the number of bytes sent or received for this transaction. dw2 31 to 24 reserved - - - 23 to 8 datastart address[15:0] sw ? writes - data start address : this is the start address for data that will be sent on or received from the usb bus. this is the internal memory address and not the cpu address. 7to0 frame[7:0] sw ? writes - frame : bits 7 to 3 is the polling rate in milliseconds. polling rate is defined as 2 (b ? 1) sof; where b = 4 to 16. executed every millisecond when b is 4. see tab l e 8 8 . dw1 63 to 57 hubaddress[6:0] sw ? writes - hub address : this indicates the hub address. 56 to 50 portnumber[6:0] sw ? writes - port number : this indicates the port number of the hub or embedded tt. 49 to 48 se[1:0] sw ? writes - this depends on the endpoint type and direction. it is valid only for split transactions. tab l e 8 9 applies to start split and complete split only. 47 reserved - - - table 87. start and complete split for interrupt: bit description ?continued bit symbol access value description
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 83 of 135 isp1763a hi-speed usb otg controller 46 s sw ? writes - split : this bit indicates whether a split transaction has to be executed: 0 ? high-speed transaction 1 ? split transaction 45 to 44 eptype[1:0] sw ? writes - transaction type : 11 ? interrupt 43 to 42 token[1:0] sw ? writes - token : token pid for this transaction: 00 ? out 01 ? in 41 to 35 deviceaddress [6:0] sw ? writes - device address : this is the usb address of the function containing the endpoint that is referred to by this buffer. 34 to 32 endpt[3:1] sw ? writes - endpoint : this is the usb address of the endpoint within the function. dw0 31 endpt[0] sw ? writes - endpoint : this is the usb address of the endpoint within the function. 30 to 29 reserved - - - 28 to 18 maxpacket length[10:0] sw ? writes - maximum packet length : this field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. the maximum packet size for the full-speed and low-speed devices is 64 bytes as defined in universal serial bus specification rev. 2.0 . 17 to 3 nrbytesto transfer[14:0] sw ? writes - number of bytes to transfer : this field indicates the number of bytes that can be transferred by this data structure. it is used to indicate the depth of the data field. the maximum total number of bytes for this transaction is 4 kb. 2to1 reserved - - - 0v sw ? sets hw ? resets - valid : 0 ? this bit is deactivated when the entire ptd is executed, or when a fatal error is encountered. 1 ? the software updates to one when there is payload to be sent or received. the current ptd is active. table 87. start and complete split for interrupt: bit description ?continued bit symbol access value description table 88. microframe description b rate frame[7:3] 52ms00001 6 4 ms 0 0010 or 0 0011 7 8 ms 0 0100 or 0 0111 8 16 ms 0 1000 or 0 1111 9 32 ms 1 0000 or 1 1111 table 89. se description interrupt se1 se0 remark i/o 1 0 low-speed i/o 0 0 full-speed
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 84 of 135 isp1763a hi-speed usb otg controller 11. peripheral controller-specific registers 11.1 register access register access depends on the bus width used. the isp1763a uses an 8-bit or 16-bit bus access. for single-byte registers, the upper byte (msbyte) must be ignored. endpoint-specific registers are indexed using the endpoint index register. the target endpoint must be selected before accessing the following registers: ? control function ? data port table 90. peripheral controller-specific register overview address register reset value reference initialization registers 00h address 00h section 11.2.1 on page 85 0ch mode 0000h section 11.2.2 on page 85 10h interrupt configuration fch section 11.2.3 on page 86 14h dcinterruptenable 0000 0000h section 11.2.4 on page 87 data flow registers 2ch endpoint index 20h section 11.3.1 on page 89 28h control function 00h section 11.3.2 on page 90 20h data port 0000h section 11.3.3 on page 91 1ch buffer length 0000h section 11.3.4 on page 92 1eh dcbufferstatus 00h section 11.3.5 on page 93 04h endpoint maxpacketsize 0000h section 11.3.6 on page 93 08h endpoint type 0000h section 11.3.7 on page 94 dma registers 30h dma command ffh section 11.4.1 on page 96 34h dma transfer counter 0000 0000h section 11.4.2 on page 97 38h dcdmaconfiguration 0001h section 11.4.3 on page 98 3ch dma hardware 04h section 11.4.4 on page 99 50h dma interrupt reason 0000h section 11.4.5 on page 99 54h dma interrupt enable 0000h section 11.4.6 on page 100 58h dma endpoint 00h section 11.4.7 on page 101 64h dma burst counter 0004h section 11.4.8 on page 102 general registers 18h dcinterrupt 0000 0000h section 11.5.1 on page 102 70h chip id 0017 6320h section 11.5.2 on page 104 74h frame number 0000h section 11.5.3 on page 104 78h scratch 0000h section 11.5.4 on page 105 7ch unlock device - section 11.5.5 on page 105 80h interrupt pulse width 1eh section 11.5.6 on page 106 84h test mode 00h section 11.5.7 on page 106
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 85 of 135 isp1763a hi-speed usb otg controller ? buffer length ? dcbufferstatus ? endpoint maxpacketsize ? endpoint type remark: all reserved bits are not implemented. the bus and bus reset values are not defined. therefore, writing to these reserved bits will have no effect. 11.2 initialization registers 11.2.1 address register this register sets the usb assigned address and enables the usb peripheral. table 91 shows the bit allocation of the register. the devaddr[6:0] bits will be cleared whenev er a bus reset, a power-on reset, or a soft reset occurs. the deven bit will be cleared whenever a power-on reset or a soft reset occurs, and will remain unchanged on a bus reset. in response to standard usb request set_address, the firmware must write the (enabled) peripheral address to the address register, followed by sending an empty packet to the host. the new peripheral address is activated when the peripheral receives acknowledgment from the host for the empty packet token. 11.2.2 mode register this register consists of 2 bytes (bit allocation: see ta b l e 9 3 ). the mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset, and clock signals. table 91. addr - address register (address 00h) bit allocation bit 7 6 5 4 3 2 1 0 symbol deven devaddr[6:0] reset 00000000 bus reset unchanged0000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 92. addr - address register (address 00h) bit description bit symbol description 7 deven device enable : logic 1 enables the device. the device will not respond to the host, unless this bit is set. 6 to 0 devaddr[6:0] device address : this field specifies the usb device peripheral. table 93. mode - mode register (address 0ch) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] dmaclk on vbusstat reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 86 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. 11.2.3 interrupt configuration register this 1 byte register determines the behavior and polarity of the int output. the bit allocation is shown in table 95 . when the usb sie receives or generates an ack, nak, or nyet, it will generate interrupts depending on three debug mode fields. cdbgmod[1:0] ? interrupts for control endpoint 0 ddbgmodin[1:0] ? interrupts for data in endpoints 1 to 7 ddbgmodout[1:0] ? interrupts for data out endpoints 1 to 7 bit 7 6 5 4 3 2 1 0 symbol clkaon sndrsu gosusp sfreset glintena wkupcs reserved [1] reset 00000000 bus reset 0 0 0 0 unchanged 0 0 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 94. mode - mode register (address 0ch) bit description bit symbol description 15 to 10 - reserved 9 dmaclkon dma clock on : 1 ? supply clock to the dma circuit. 0 ? power saving mode. the dma circuit will stop completely to save power. 8 vbusstat v bus status : this bit reflects the v bus pin status when the otg_disable bit is logic 1. 7 clkaon clock always on : 1 ? enable the clock-always-on feature. 0 ? disable the clock-always-on feature. when the clock-always-on feature is disabled, a gosusp event can stop the clock. the clock is stopped after a delay of approximately 2 ms. therefore, the peripheral controller will consume less power. if the clock-always-on feature is enabled, clocks are always running and the gosusp event is unable to stop the clock while the peripheral controller enters the suspend state. 6 sndrsu send resume : writing logic 1, followed by logic 0 will generate an upstream resume signal of 10 ms duration, after a 5 ms delay. 5 gosusp go suspend : writing logic 1, followed by logic 0 will activate suspend mode. 4 sfreset soft reset : writing logic 1, followed by logic 0 will enable a software-initiated reset to the isp1763a. a soft reset is similar to a hardware-initiated reset using the reset_n pin. 3glintena global interrupt enable : logic 1 enables all interrupts. individual interrupts can be masked by clearing the corresponding bits in the dcinterruptenable register. when this bit is not set, an unmasked interrupt will not generate an interrupt trigger on the interrupt pin. if the global interrupt, however, is enabled while there is any pending unmasked interrupt, an interrupt signal will immediately be generated on the interrupt pin. if the interrupt is set to pulse mode, the interrupt events that were generated before the global interrupt is enabled may be dropped. 2 wkupcs wake up on chip select : logic 1 enables wake-up through a valid register read on the isp1763a. a read will invoke the chip clock to restart. a write to the register before the clock is stable may cause malfunctioning. 1 to 0 - reserved
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 87 of 135 isp1763a hi-speed usb otg controller the debug mode settings for cdbgmod, ddbgmodin, and ddbgmodout allow you to individually configure when the isp1763a sends an interrupt to the external microprocessor. ta b l e 9 7 lists available combinations. bit intpol controls the signal polarity of the int output: active high or low, rising or falling edge. for level-triggering, bit intlvl must be made logic 0. by setting intlvl to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering). [1] first nak: the first nak on an in or out token after a previous ack response. 11.2.4 dcinterruptenable register this register enables or disables individual interrupt sources. the interrupt for each endpoint can individually be controlled through the associated iepnrx or iepntx bits, here n represents the endpoint number. all interrupts can globally be disabled through bit glintena in the mode register (see ta b l e 9 3 ). an interrupt is generated when the usb sie receives or generates an ack or nak on the usb bus. the interrupt generation depends on debug mode settings of bit fields cdbgmod[1:0], ddbgmodin[1:0], and ddbgmodout[1:0]. table 95. intr_conf - interrupt configuration register (a ddress 10h) bit allocation bit 7 6 5 4 3 2 1 0 symbol cdbgmod[1:0] ddbgmodin[1:0] ddbgmodout[1:0] intlvl intpol reset 11111100 bus reset 1 1 1 1 1 1 unchanged unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 96. intr_conf - interrupt configuration register (a ddress 10h) bit description bit symbol description 7 to 6 cdbgmod[1:0] control 0 debug mode : for values, see ta bl e 9 7 . 5 to 4 ddbgmodin[1:0] data debug mode in : for values, see ta b l e 9 7 . 3 to 2 ddbgmodout[1:0] data debug mode out : for values, see table 97 . 1intlvl interrupt level : selects signaling mode on output int: 0 = level; 1 = pulsed. in pulsed mode, an interrupt produces a 60 ns pulse. bus reset value: unchanged. remark: value written to this bit must be the same as the value written to bit intr_level in the hw mode control register (address b6h). 0 intpol interrupt polarity : selects the signal polarity on output int; 0 = active low; 1 = active high. bus reset value: unchanged. remark: value written to this bit must be the same as the value written to bit intr_pol in the hw mode control register (address b6h). table 97. debug mode settings value cdbgmod ddbgmodin ddbgmodout 00h interrupt on all ack and nak interrupt on all ack and nak interrupt on all ack, nyet, and nak 01h interrupt on all ack interrupt on ack interrupt on ack and nyet 1xh interrupt on all ack and first nak [1] interrupt on all ack and first nak [1] interrupt on all ack, nyet, and first nak [1]
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 88 of 135 isp1763a hi-speed usb otg controller all data in transactions use transmit buffers (tx) that are handled by ddbgmodin bits. all data out transactions go through receive buffers (rx) that are handled by ddbgmodout bits. transactions on control endpoint 0 (in, out, and setup) are handled by cdbgmod bits. interrupts caused by events on the usb bus (sof, suspend, resume, bus reset, set up, and high-speed status) can also be individually controlled. a bus reset disables all enabled interrupts, except bit iebrst (bus reset) that remains unchanged. the dcinterruptenable register consists of 4 bytes. the bit allocation is given in table 98 . [1] the reserved bits should always be written with the reset value. table 98. dcinterruptenable - device controller interrupt enable register (address 14h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] iep7tx iep7rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol iep6tx iep6rx iep5tx iep5rx iep4tx iep4rx iep3tx iep3rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol iep2tx iep2rx iep1tx iep1rx iep0tx iep0rx reserved [1] iep0setup reset 000000- 0 bus reset 000000- 0 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ievbus iedma iehs_sta ieresm iesusp iepsof iesof iebrst reset 00000000 bus reset 0 0 0 0 0 0 0 unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 99. dcinterruptenable - device controller interrupt enable register (address 14h) bit description bit symbol description 31 to 26 - reserved 25 iep7tx interrupt enable endpoint 7 transmit : logic 1 enables interrupt from the indicated endpoint. 24 iep7rx interrupt enable endpoint 7 receive : logic 1 enables interrupt from the indicated endpoint. 23 iep6tx interrupt enable endpoint 6 transmit : logic 1 enables interrupt from the indicated endpoint. 22 iep6rx interrupt enable endpoint 6 receive : logic 1 enables interrupt from the indicated endpoint. 21 iep5tx interrupt enable endpoint 5 transmit : logic 1 enables interrupt from the indicated endpoint. 20 iep5rx interrupt enable endpoint 5 receive : logic 1 enables interrupt from the indicated endpoint. 19 iep4tx interrupt enable endpoint 4 transmit : logic 1 enables interrupt from the indicated endpoint. 18 iep4rx interrupt enable endpoint 4 receive : logic 1 enables interrupt from the indicated endpoint.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 89 of 135 isp1763a hi-speed usb otg controller 11.3 data flow registers 11.3.1 endpoint index register the endpoint index register selects a target endpoint for register access by the microcontroller. the register consists of 1 byte, and the bit allocation is shown in ta b l e 1 0 0 . the following registers are indexed: ? control function ? data port ? buffer length ? dcbufferstatus ? endpoint maxpacketsize ? endpoint type for example, to access the out data buffer of endpoint 1 using the data port register, the endpoint index register must be written first with 02h. remark: the endpoint index register and the dma endpoint register must not point to the same endpoint, irrespective of in and out. remark: after writing to the endpoint index register, wait for 400 ns before accessing any register. 17 iep3tx interrupt enable endpoint 3 transmit : logic 1 enables interrupt from the indicated endpoint. 16 iep3rx interrupt enable endpoint 3 receive : logic 1 enables interrupt from the indicated endpoint. 15 iep2tx interrupt enable endpoint 2 transmit : logic 1 enables interrupt from the indicated endpoint. 14 iep2rx interrupt enable endpoint 2 receive : logic 1 enables interrupt from the indicated endpoint. 13 iep1tx interrupt enable endpoint 1 transmit : logic 1 enables interrupt from the indicated endpoint. 12 iep1rx interrupt enable endpoint 1 receive : logic 1 enables interrupt from the indicated endpoint. 11 iep0tx interrupt enable endpoint 0 transmit : logic 1 enables interrupt from the control in endpoint 0. 10 iep0rx interrupt enable endpoint 0 receive : logic 1 enables interrupt from the control out endpoint 0. 9 - reserved 8 iep0setup interrupt enable endpoint 0 set-up : logic 1 enables interrupt for the set-up data received on endpoint 0. 7 ievbus interrupt enable v bus : logic 1 enables interrupt when there is a polarity change on v bus . 6iedma interrupt enable dma : logic 1 enables interrupt on detecting a dma status change. 5 iehs_sta interrupt enable high-speed status : logic 1 enables interrupt on detecting a high-speed status change. 4 ieresm interrupt enable resume : logic 1 enables interrupt on detecting a resume state. 3 iesusp interrupt enable suspend : logic 1 enables interrupt on detecting a suspend state. 2 iepsof interrupt enable pseudo sof : logic 1 enables interrupt on detecting a pseudo sof. 1 iesof interrupt enable sof : logic 1 enables interrupt on detecting an sof. 0 iebrst interrupt enable bus reset : logic 1 enables interrupt on detecting a bus reset. table 99. dcinterruptenable - device controller interrupt enable register (address 14h) bit description ?continued bit symbol description
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 90 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. 11.3.2 control function register the control function register performs the buffer management on endpoints. it consists of 1 byte, and the bit allocation is given in table 103 . the register bits can stall, clear, or validate any enabled data endpoint. before accessing this register, the endpoint index register must be written first to specify the target endpoint. [1] the reserved bits should always be written with the reset value. table 100. endp_index - endpoint index register (address 2ch) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved [1] ep0setup reserved [1] endpidx[2:0] dir reset 00 100000 bus reset 00 100000 access r/w r/w r/w r/w r/w r/w r/w r/w table 101. endp_index - endpoint index register (address 2ch) bit description bit symbol description 7 to 6 - reserved 5 ep0setup endpoint 0 set up : selects the set-up token buffer for endpoint 0. must be logic 0 for access to endpoints other than the set-up token buffer. 0 ? any buffer other than the set-up token buffer. this means control in endpoint, control out endpoint, data in endpoint, and data out endpoint. 1 ? set-up token buffer 4 - reserved 3 to 1 endpidx[2:0] endpoint index : selects the target endpoint buffer. 0dir direction : sets the target endpoint as in or out. 0 ? target endpoint refers to out (rx) fifo. 1 ? target endpoint refers to in (tx) fifo. table 102. addressing of endpoint buffers buffer name ep0setup endpidx dir setup 1 00h 0 control out 0 00h 0 control in 0 00h 1 data out 0 0xh 0 data in 0 0xh 1 table 103. ctrl_func- control function register (address 28h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved [1] clbuf vendp dsen status stall reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 91 of 135 isp1763a hi-speed usb otg controller 11.3.3 data port register this 2-byte register provides direct access for a microcontroller to the fifo of the indexed endpoint. the bit allocation is shown in table 105 . peripheral to host (in endpoint) : after each write, an internal counter is automatically incremented, by two in 16-bit mode and one in 8-bit mode, to the next location in the tx fifo. when all bytes have been written (fifo byte count = endpoint maxpacketsize), the buffer is automatically validated. the data packet will then be sent on the next in token. whenever required, the control function register (bit vendp) can validate the endpoint whose byte count is less than maxpacketsize. remark: the buffer can be automatically validated or cleared by using the buffer length register (see ta b l e 1 0 6 ). host to peripheral (out endpoint) : after each read, an internal counter is automatically decremented, by two in 16-bit mode and one in 8-bit mode, to the next location in the rx fifo. when all bytes have been read, the buffer contents are automatically cleared. a table 104. ctrl_func- control function register (address 28h) bit description bit symbol description 7 to 5 - reserved 4clbuf clear buffer : logic 1 clears the rx buffer of the indexed endpoint. the rx buffer is automatically cleared once the endpoint is completely read. this bit is set only when it is necessary to forcefully clear the buffer. remark: if using a double buffer, to clear both the buffers, issue the clbuf command two times, that is, set and clear this bit two times. 3 vendp validate endpoint : logic 1 validates data in the tx fifo of an in endpoint for sending on the next in token. in general, the endpoint is automatically validated when its fifo byte count has reached endpoint maxpacketsize. this bit is set only when it is necessary to validate the endpoint with the fifo byte count that is below the endpoint maxpacketsize. 2 dsen data stage enable : this bit controls the response of the isp1763a to a control transfer. after the completion of the set-up stage, the firmware must determine whether a data stage is required. for control out, the firmware will set this bit and the isp1763a goes into the data stage. otherwise, the isp1763a will nak the data stage transfer. for control in, the firmware will set this bit before writing data to the tx fifo and validate the endpoint. if no data stage is required, the firmware can immediately set the status bit after the set-up stage. 1status status acknowledge : only applicable for control in and out. this bit controls the generation of ack or nak during the status stage of a setup transfer. it is automatically cleared when the status stage is completed and a setup token is received. no interrupt signal will be generated. 0 ? sends nak 1 ? sends an empty packet following the in token (peripheral-to-host) or ack following the out token (host-to-peripheral) remark: the status bit is cleared to zero once the zero-length packet is acknowledged by the device or the pc host. remark: data transfers preceding the status stage must first be fully completed before the status bit can be set. 0stall stall endpoint : logic 1 stalls the indexed endpoint. this bit is not applicable for isochronous transfers. remark: stalling a data endpoint will confuse the data toggle bit about the stalled endpoint because the internal logic picks up from where it is stalled. therefore, the data toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit enable to logic 0, followed by logic 1 in the endpoint type register) to reset the pid.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 92 of 135 isp1763a hi-speed usb otg controller new data packet can then be received on the next out token. buffer contents can also be cleared through the control function register (bit clbuf), whenever it is necessary to forcefully clear contents. the data port register description when the isp1763a is in 16-bit mode is given in ta b l e 1 0 5 . 11.3.4 buffer length register this register determines the current packet size (datacount) of the indexed endpoint fifo. the bit allocation is given in table 106 . the buffer length register will be updated with the fifo size register value whenever there is a write access to the endpoint maxpacketsize register (see ta b l e 1 0 9 ). a smaller value can be written when required. after a bus reset, the buffer length register is made zero. in endpoint : when the data transfer is performed in multiples of maxpacketsize, the buffer length register is not significant. this register is useful only when transferring data that is not a multiple of maxpacketsize. the following two examples demonstrate the significance of the buffer length register. example 1: consider that the transfer size is 512 bytes and maxpacketsize is programmed as 64 bytes, the buffer length register need not be filled. this is because the transfer size is a multiple of maxpacketsize, and maxpacketsize packets will be automatically validated because the last packet is also of maxpacketsize. example 2: consider that the transfer size is 510 bytes and maxpacketsize is programmed as 64 bytes, the buffer length register should be filled with 62 bytes just before the microcontroller writes the last packet of 62 bytes. this ensures that the last packet, which is a short packet of 62 bytes, is automatically validated. use the vendp bit in the control register if you are not using the buffer length register. this is applicable only to the pio mode access. out endpoint : the datacount value is automatically initialized to the number of data bytes sent by the host on each ack. remark: when using a 16-bit microprocessor bus, the last byte of an odd-sized packet is output as the lower byte (lsbyte). table 105. data_port - data port register (address 20h) bit description legend: * reset value bit symbol access value description 15 to 0 dataport [15:0] r/w 0000h* data port : a 500 ns delay starting from the reception of the endpoint interrupt may be required for the first read from the data port. table 106. buffer_length - buffer length register (address 1ch) bit description legend: * reset value bit symbol access value description 15 to 0 datacount [15:0] r/w 0000h* data count : determines the current packet size of the indexed endpoint fifo.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 93 of 135 isp1763a hi-speed usb otg controller 11.3.5 dcbufferstatus register the endpoint index must first be set before accessing this register for the corresponding endpoint. it reflects the status of the endpoint fifo. table 107 shows the bit allocation of the dcbufferstatus register. remark: buffer 1 is filled first before filling up buffer 0. remark: this register is not applicable to the control endpoint. remark: for the endpoint in data transfer, the firmware must ensure a 200 ns delay between writing of the data packet and reading the dcbufferstatus register. for the endpoint out data transfer, the firmware must also ensure a 200 ns delay between the reception of the endpoint interrupt and reading the dcbufferstatus register. 11.3.6 endpoint maxpacketsize register this register determines the maximum packet size for all endpoints, except control endpoint 0. the register contains 2 bytes, and the bit allocation is given in table 109 . each time the register is written, the buffer length registers of the corresponding endpoint is re-initialized to the ffosz field value. ntrans bits control the number of transactions allowed in a single microframe for high-speed isochronous and interrupt endpoints only. table 107. dcbufferstatus - device controller buffer status register (address 1eh) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved buf1 buf0 reset 00000000 bus reset 00000000 access rrrrrrrr table 108. dcbufferstatus - device controller buffer status register (address 1eh) bit description bit symbol description 7 to 2 - reserved 1 to 0 buf[1:0] buffer : 00 ? the buffers are not filled. 01 ? one of the buffers is filled. 10 ? one of the buffers is filled. 11 ? both the buffers are filled. table 109. endp_maxpktsize - endpoint maxpacketsize register (address 04h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] ntrans[1:0] ffosz[10:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ffosz[7:0]
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 94 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. the isp1763a supports all the transfers given in universal serial bus specification rev. 2.0 . each programmable fifo can be independently configured using its endpoint maxpacketsize register (r/w: 04h), but the total physical size of all enabled endpoints (in plus out), including the set-up token buffer, control in, and control out, must not exceed 4096 bytes. 11.3.7 endpoint type register this register sets the endpoint type of the indexed endpoint: isochronous, bulk, or interrupt. it also serves to enable the endpoint and configure it for double buffering. automatic generation of an empty packet for a zero-length tx buffer can be disabled using bit noempkt. the register contains 2 bytes. see table 111 . [1] the reserved bits should always be written with the reset value. reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 table 110. endp_maxpktsize - endpoint maxpacket size register (address 04h) bit description bit symbol description 15 to 13 - reserved 12 to 11 ntrans[1:0] number of transactions : hs mode only. 00 ? one packet per microframe. 01 ? two packets per microframe. 10 ? three packets per microframe. 11 ? reserved these bits are applicable only for isochronous or interrupt transactions. 10 to 0 ffosz[10:0] fifo size : sets the fifo size in bytes for the indexed endpoint. applies to both high-speed and full-speed operations (see ta b l e 111 ). table 111. endp_type - endpoint type register (address 08h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] noempkt enable dblbuf endptyp[1:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 95 of 135 isp1763a hi-speed usb otg controller 11.4 dma registers the generic dma (gdma) transfer can be done by writing the proper opcode in the dma command register. the control bits are given in table 113 . gdma read/write (opcode = 00h/01h) for generic dma slave mode the gdma (slave) can operate in counter mode. rd_n/ds_n/re_n/oe_n and wr_n/rw_n/we_n are dma data strobe signals. these signals are also used as data strobe signals during the pio access. an internal multiplex will redirect these signals to the dma controller for the dma transfer or to registers for the pio access. in counter mode, the dis_xfer_cnt bit in the dcdmaconfiguration register must be set to logic 0. the dma transfer counter register must be programmed before any dma command is issued. the dma transfer counter is set by writing from the lsbyte to the msbyte (address: 34h to 37h). the internal dma transfer counter is updated when the msbyte is written. once the dma transfer is started, the transfer counter starts decrementing and on reaching 0, the dma_xfer_ok bit is set and an interrupt is generated by the isp1763a. the dma transfer starts once the dma command is issued. any of the following three ways will terminate this dma transfer: ? detecting an internal eot (short packet on an out token) ? resetting the dma ? gdma stop command there are two interrupts that are programmable to differentiate the method of dma termination: the int_eot and dma_xfer_ok bits in the dma interrupt reason register. for details, see table 123 . table 112. endp_type - endpoint type register (address 08h) bit description bit symbol description 15 to 5 - reserved 4 noempkt no empty packet : logic 0 causes the isp1763a to return a null length packet for the in token after the dma in transfer is complete. set to logic 1 to disable the generation of the null length packet. 3 enable endpoint enable : logic 1 enables the fifo of the indexed endpoint. the memory size is allocated as specified in the endpoint maxpacketsize register. logic 0 disables the fifo. remark: stalling a data endpoint will confuse the data toggle bit on the stalled endpoint because the internal logic picks up from where it has stalled. therefore, the data toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit enable to logic 0, followed by logic 1 in the endpoint type register) to reset the pid. 2 dblbuf double buffering : logic 1 enables double buffering for the indexed endpoint. logic 0 disables double buffering. 1 to 0 endptyp [1:0] endpoint type : these bits select the endpoint type as follows. 00 ? not used 01 ? isochronous 10 ? bulk 11 ? interrupt
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 96 of 135 isp1763a hi-speed usb otg controller remark: the dma bus defaults to 3-state, until a dma command is executed. all the other control signals are not 3-stated. 11.4.1 dma command register the dma command register is a 1-byte register (for bit allocation, see table 114 ) that initiates all dma transfer activities on the dma controller. the register is write-only; reading it will return ffh. remark: the dma bus will be in 3-state until a dma command is executed. table 113. control bits for gdma read/write (opcode = 00h/01h) control bits description reference dcdmaconfiguration register mode[1:0] determines the active read or write data strobe signals ta bl e 11 9 width selects the dma bus width: 16 or 8 bits dis_xfer_cnt disables the use of the dma transfer counter dma hardware register ack_pol, dreq_pol select the polarity of the dma handshake signals table 122 table 114. dma_cmd - dma command register (address 30h) bit allocation bit 7 6 5 4 3 2 1 0 symbol dma_cmd[7:0] reset 11111111 bus reset 11111111 access wwwwwwww table 115. dma_cmd - dma command register (address 30h) bit description bit symbol description 7 to 0 dma_cmd[7:0] dma command code; see table 116 . table 116. dma commands code name description 00h gdma read generic dma in token transfer : data is transferred from the external dma bus to the internal buffer. 01h gdma write generic dma out token transfer : data is transferred from the internal buffer to the external dma bus. 02h to 0dh - reserved 0eh validate buffer validate buffer : request from the microcontroller to validate the endpoint buffer, following a dma-to-usb data transfer. 0fh clear buffer clear buffer : request from the microcontroller to clear the endpoint buffer, after a dma-to-usb data transfer. it clears the tx buffer of the indexed endpoint; the rx buffer is not affected. the tx buffer is automatically cleared once data is sent on the usb bus. this command is issued only when it is necessary to forcefully clear the buffer. remark: if using a double buffer, to clear both the buffers, issue the clear buffer command two times. 10h - reserved
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 97 of 135 isp1763a hi-speed usb otg controller 11.4.2 dma transfer counter register this 4-byte register sets up the total byte count for a dma transfer (dmacr). it indicates the remaining number of bytes left for transfer. the bit allocation is given in table 117 . for in endpoint ? because there is a fifo in the isp1763a dma controller, some data may remain in the fifo during the dma transfer. the maximum fifo size is 8 bytes, and the maximum delay time for data to be shifted to endpoint buffer is 60 ns. for out endpoint ? data will not be cleared for the endpoint buffer until all the data has been read from the dma fifo. 11h reset dma reset dma : initializes the dma core to its power-on reset state. remark: when the dma core is reset during the reset dma command, the dreq, dack, rd_n/ds_n/re_n/oe_n, and wr_n/rw_n/we_n handshake pins will temporarily be asserted. this can confuse the external dma controller. to prevent this, start the external dma controller only after the dma reset. 12h - reserved 13h gdma stop gdma stop : this command stops the gdma data transfer. any data in the out endpoint that is not transferred by the dma will remain in the buffer. the fifo data for the in endpoint will be written to the endpoint buffer. an interrupt bit will be set to indicate that the dma stop command is complete. 14h to ffh - reserved table 116. dma commands ?continued code name description table 117. dma_xfr_ctr - dma transfer counter register (address 34h) bit allocation bit 31 30 29 28 27 26 25 24 symbol dmacr4 = dmacr[31:24] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol dmacr3 = dmacr[23:16] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol dmacr2 = dmacr[15:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dmacr1 = dmacr[7:0] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 98 of 135 isp1763a hi-speed usb otg controller 11.4.3 dcdmaconfiguration register this register defines the dma configuration for gdma mode. the dcdmaconfiguration register consists of 2 bytes. the bit allocation is given in table 119 . [1] the reserved bits should always be written with the reset value. [1] the dreq pin will be driven only after you perform a write access to the dcdmaconfiguration register (that is, after you hav e configured the dcdmaconfiguration register). table 118. dma_xfr_ctr - dma transfer counter register (address 34h) bit description bit symbol description 31 to 24 dmacr4, dmacr[31:24] dma counter 4 : dma transfer counter byte 4 (msb) 23 to 16 dmacr3, dmacr[23:16] dma counter 3 : dma transfer counter byte 3 15 to 8 dmacr2, dmacr[15:8] dma counter 2 : dma transfer counter byte 2 7 to 0 dmacr1, dmacr[7:0] dma counter 1 : dma transfer counter byte 1 (lsb) table 119. dcdmaconfiguration - device controller direct memory access configuration register (address 38h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol dis_xfer_ cnt reserved [1] mode[1:0] reserved [1] width reset 00000001 bus reset 00000001 access r/w r/w r/w r/w r/w r/w r/w r/w table 120. dcdmaconfiguration - device controller direct memory access configuration register (address 38h) bit description bit [1] symbol description 15 to 8 - reserved 7 dis_xfer_cnt disable transfer counter : write logic 0 to perform dma operation. logic 1 disables the dma transfer counter (see table 117 ). 6 to 4 - reserved 3 to 2 mode[1:0] mode : 00 ? wr_n/rw_n/we_n slave strobes data from the dma bus into the isp1763a; rd_n/ds_n/re_n/oe_n slave puts data from the isp1763a on the dma bus 01, 10, 11 ? reserved 1 - reserved 0width width : this bit selects the dma bus width for the gdma slave. 0 ? 8-bit data bus 1 ? 16-bit data bus remark: both this bit and bit data_bus_width must be configured with the same bus width, for example, 16 bits or 8 bits.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 99 of 135 isp1763a hi-speed usb otg controller 11.4.4 dma hardware register this register defines the dma configuration for gdma mode. the bit allocation is given in ta b l e 1 2 1 . [1] the reserved bits should always be written with the reset value. 11.4.5 dma interrupt reason register this 2-byte register shows the source(s) of the dma interrupt. each bit is refreshed after a dma command is executed. an interrupt source is cleared by writing logic 1 to the corresponding bit. on detecting the interrupt, the external microprocessor must read the dma interrupt reason register and mask it with the corresponding bits in the dma interrupt enable register to determine the source of the interrupt. the bit allocation is given in table 123 . table 121. dma_hw - dma hardware register (address 3ch) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved [1] dack_ pol dreq_ pol reserved [1] reset 00000100 bus reset 00000100 access r/w r/w r/w r/w r/w r/w r/w r/w table 122. dma_hw - dma hardware register (address 3ch) bit description bit symbol description 7 to 4 reserved 3 dack_pol dack polarity : selects the dma acknowledgment polarity. 0 ? dack is active low. 1 ? dack is active high. remark: value written to this bit must be the same as the value written to bit dack_pol in the hw mode control register (address b6h). 2 dreq_pol dreq polarity : selects the dma request polarity. 0 ? dreq is active low. 1 ? dreq is active high. remark: value written to this bit must be the same as the value written to bit dreq_pol in the hw mode control register (address b6h). 1to0 - reserved table 123. dma_intr_reason - dma interrupt reason register (address 50h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] gdma_ stop reserved [1] int_eot reserved [1] dma_ xfer_ok reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 100 of 135 isp1763a hi-speed usb otg controller [1] the reserved bits should always be written with the reset value. ta b l e 1 2 6 shows the status of the bits in the dma interrupt reason register when the corresponding bits in the dcinterrupt register are set. [1] 1 indicates that the bit is set and 0 indicates that the bit is not set. a bit is set when the corresponding eot condition is met. [2] the value of int_eot may not be accurate if an exter nal or internal transfer c ounter is programmed with a value that is lower than the transfer that the host requests. to terminate an out transfer with int_eot, the external or internal dma counter should be programmed as a multiple of the full-packet length of the dma endpoint. when a short packet is successfully transferred by dma, int_eot is set. 11.4.6 dma interrupt enable register this 2-byte register controls the interrupt generation of the source bits in the dma interrupt reason register. the bit allocation is given in table 127 . bit 7 6 5 4 3 2 1 0 symbol reserved [1] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 124. dma_intr_reason - dma interrupt reason register (address 50h) bit description bit symbol description 15 to 13 - reserved 12 gdma_stop gdma stop : when the gdma_stop command is issued to the dma command register, it means that the dma transfer has successfully terminated. 11 - reserved 10 int_eot internal eot : logic 1 indicates that an internal eot is detected; see tab l e 1 25 . 9 - reserved 8dma_xfer_ok dma transfer ok : logic 1 indicates that the dma transfer has been completed, that is, dma transfer counter has become zero. 7 to 0 - reserved table 125. internal eot-functional relation with bit dma_xfer_ok int_eot dma_xfer_ok description 1 0 during the dma transfer, there is a premature termination with a short packet. 1 1 dma transfer is completed with a short packet. the dma transfer counter has reached 0. 0 1 dma transfer is completed without any short packet. the dma transfer counter has reached 0. table 126. status of the bits in the dma interrupt reason register status int_eot [1] dma_xfer_ok [1] counter enabled counter disabled in full 0 1 0 in short 0 1 0 out full 0 1 0 out short 1 [2] 10
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 101 of 135 isp1763a hi-speed usb otg controller logic 1 enables the interrupt generation. the values after a (bus) reset are logic 0 (disabled). [1] the reserved bits should always be written with the reset value. 11.4.7 dma endpoint register this 1-byte register selects a usb endpoint fifo as a source or destination for dma transfers. the bit allocation is given in table 129 . [1] the reserved bits should always be written with the reset value. table 127. dma_intr_en - dma interrupt enable register (address 54h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] ie_gdma_ stop reserved [1] ie_int_ eot reserved [1] ie_dma_ xfer_ok reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol reserved [1] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 128. dma_intr_en - dma interrupt enable register (address 54h) bit description bit symbol description 15 to 13 - reserved 12 ie_gdma_stop interrupt enable gdma stop : logic 1 enables the gdma stop interrupt. 11 - reserved 10 ie_int_eot interrupt enable internal eot : logic 1 enables the internal eot interrupt. 9 - reserved 8 ie_dma_xfer_ok interrupt enable dma transfer ok : logic 1 enables the dma transfer complete interrupt. 7 to 0 - reserved table 129. dma_endp - dma endpoint register (address 58h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved [1] epidx[2:0] dmadir reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 102 of 135 isp1763a hi-speed usb otg controller the dma endpoint register must not reference the endpoint that is indexed by the endpoint index register (2ch) at any time. doing so will result in data corruption. therefore, if the dma endpoint register is unused, point it to an unused endpoint. if the dma endpoint register, however, is pointed to an active endpoint, the firmware must not reference the same endpoint on the endpoint index register. 11.4.8 dma burst counter register ta b l e 1 3 1 shows the bit allocation of the register. [1] the reserved bits should always be written with the reset value. 11.5 general registers 11.5.1 dcinterrupt register the dcinterrupt register consists of 4 bytes. the bit allocation is given in table 133 . table 130. dma_endp - dma endpoint register (address 58h) bit description bit symbol description 7 to 4 - reserved 3 to 1 epidx[2:0] endpoint index : selects the indicated endpoint for the dma access 0dmadir dma direction : 0 ? selects the rx/out fifo for dma read transfers. 1 ? selects the tx/in fifo for dma write transfers. table 131. dma_brst_ctr - dma burst counter register (address 64h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved [1] burstcounter[12:8] reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol burstcounter[7:0] reset 00000100 bus reset 00000100 access r/w r/w r/w r/w r/w r/w r/w r/w table 132. dma_brst_ctr - dma burst counter register (address 64h) bit description bit symbol description 15 to 13 - reserved 12 to 0 burst counter [12:0] burst counter : this register defines the burst length. the counter must be programmed to be a multiple of two in 16-bit mode and one in 8-bit mode. the value of the burst counter must be programmed so that the buffer counter is a factor of the burst counter. dreq will drop when the number of bytes transferred equals to the burst counter at every dma read or write cycle.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 103 of 135 isp1763a hi-speed usb otg controller when a bit is set in the dcinterrupt register, it indicates that the hardware condition for an interrupt has occurred. when the dcinterrupt register content is non-zero, the int output will be asserted. on detecting the interrupt, the external microprocessor must read the dcinterrupt register to determine the source of the interrupt. each endpoint buffer has a dedicated interrupt bit (epntx, epnrx). in addition, various bus states can generate an interrupt: resume, suspend, pseudo sof, sof, and bus reset. the dma controller has only one interrupt bit: the source for a dma interrupt is shown in the dma interrupt reason register. each interrupt bit can individually be cleared by writing logic 1. the dma interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the dma interrupt reason register and writing logic 1 to the dma bit of the dcinterrupt register. [1] the reserved bits should always be written with the reset value. table 133. dcinterrupt - device controller interrupt register (address 18h) bit allocation bit 31 30 29 28 27 26 25 24 symbol reserved [1] ep7tx ep7rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 23 22 21 20 19 18 17 16 symbol ep6tx ep6rx ep5tx ep5rx ep4tx ep4rx ep3tx ep3rx reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 15 14 13 12 11 10 9 8 symbol ep2tx ep2rx ep1tx ep1rx ep0tx ep0rx reserved [1] ep0setup reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol vbus dma hs_stat resume susp psof sof breset reset 00000000 bus reset 0000000unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 134. dcinterrupt - device controller inte rrupt register (address 18h) bit description bit symbol description 31 to 26 - reserved 25 ep7tx endpoint 7 transmit : logic 1 indicates the endpoint 7 tx buffer as the interrupt source. 24 ep7rx endpoint 7 receive : logic 1 indicates the endpoint 7 rx buffer as the interrupt source. 23 ep6tx endpoint 6 transmit : logic 1 indicates the endpoint 6 tx buffer as the interrupt source. 22 ep6rx endpoint 6 receive : logic 1 indicates the endpoint 6 rx buffer as the interrupt source. 21 ep5tx endpoint 5 transmit : logic 1 indicates the endpoint 5 tx buffer as the interrupt source. 20 ep5rx endpoint 5 receive : logic 1 indicates the endpoint 5 rx buffer as the interrupt source.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 104 of 135 isp1763a hi-speed usb otg controller 11.5.2 chip id register this read-only register contains the chip identification and hardware version numbers. the firmware must check this information to determine functions and features supported. the bit allocation is shown in ta b l e 1 3 5 . 11.5.3 frame number register this read-only register contains the frame number of the last successfully received start-of-frame (sof). the register contains 2 bytes. the bit allocation is given in ta b l e 1 3 6 . 19 ep4tx endpoint 4 transmit : logic 1 indicates the endpoint 4 tx buffer as the interrupt source. 18 ep4rx endpoint 4 receive : logic 1 indicates the endpoint 4 rx buffer as the interrupt source. 17 ep3tx endpoint 3 transmit : logic 1 indicates the endpoint 3 tx buffer as the interrupt source. 16 ep3rx endpoint 3 receive : logic 1 indicates the endpoint 3 rx buffer as the interrupt source. 15 ep2tx endpoint 2 transmit : logic 1 indicates the endpoint 2 tx buffer as the interrupt source. 14 ep2rx endpoint 2 receive : logic 1 indicates the endpoint 2 rx buffer as the interrupt source. 13 ep1tx endpoint 1 transmit : logic 1 indicates the endpoint 1 tx buffer as the interrupt source. 12 ep1rx endpoint 1 receive : logic 1 indicates the endpoint 1 rx buffer as the interrupt source. 11 ep0tx endpoint 0 transmit : logic 1 indicates the endpoint 0 data tx buffer as the interrupt source. 10 ep0rx endpoint 0 receive : logic 1 indicates the endpoint 0 data rx buffer as the interrupt source. 9 - reserved 8 ep0setup endpoint 0 set-up : logic 1 indicates that a set-up token was received on endpoint 0. 7 vbus v bus : logic 1 indicates there is a polarity change on v bus . 6dma dma status : logic 1 indicates a change in the dma interrupt reason register. 5 hs_stat high-speed status : logic 1 indicates a change from full-speed to high-speed mode (hs connection). this bit is not set when the system goes into the full-speed suspend. 4 resume resume status : logic 1 indicates that a status change from suspend to resume (active) was detected. 3susp suspend status : logic 1 indicates that a status change from active to suspend was detected on the bus. 2 psof pseudo sof interrupt : logic 1 indicates that a pseudo sof or sof was received. pseudo sof is an internally generated clock signal (full-speed: 1 ms period, high-speed: 125 s period) that is not synchronized to the usb bus sof or sof. 1sof sof interrupt : logic 1 indicates that a sof or sof was received. 0 breset bus reset : logic 1 indicates that a usb bus reset was detected. table 134. dcinterrupt - device controller inte rrupt register (address 18h) bit description ?continued bit symbol description table 135. dcchipid - device controller chip identifier register (address 70h) bit description legend: * reset value bit symbol access value description 31 to 0 chipid[31:0] r 0017 6320h* chip id : this registers represents the hardware version number (20h) and the chip id (1763h) for the peripheral controller.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 105 of 135 isp1763a hi-speed usb otg controller 11.5.4 scratch register this 16-bit register can be used by the firmware to save and restore information. for example, the device status before it enters the suspend state; see table 138 . 11.5.5 unlock device register to protect registers from getting corrupted when the isp1763a goes into suspend, the write operation is disabled. in this case, when the chip resumes, the unlock device command must first be issued to this register before attempting to write to the rest of the registers. this is done by writing unlock code (aa37h) to this register. the bit allocation of the unlock device register is given in table 140 . table 136. frame_no - frame number register (address 74h) bit allocation bit 15 14 13 12 11 10 9 8 symbol reserved microsof[2:0] sofr[10:8] reset 00000000 bus reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol sofr[7:0] reset 00000000 bus reset 00000000 access rrrrrrrr table 137. frame_no - frame number register (address 74h) bit description bit symbol description 15 to 14 - reserved 13 to 11 microsof[2:0] sof received : microframe number of the last successfully received sof. 10 to 0 sofr[10:0] sof received : frame number of the last successfully received sof. table 138. scratch - scratch register (address 78h) bit allocation bit 15 14 13 12 11 10 9 8 symbol sfirh[7:0] reset 00000000 bus reset unchanged access r/w r/w r/w r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol sfirl[7:0] reset 00000000 bus reset unchanged access r/w r/w r/w r/w r/w r/w r/w r/w table 139. scratch - scratch register (address 78h) bit description bit symbol description 15 to 8 sfirh[7:0] scratch firmware information register (higher byte) 7 to 0 sfirl[7:0] scratch firmware information register (lower byte)
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 106 of 135 isp1763a hi-speed usb otg controller 11.5.6 interrupt pulse width register ta b l e 1 4 2 shows the bit description of the register. 11.5.7 test mode register this 1-byte register allows the firmware to set the dp and dm pins to predetermined states for testing purposes. the bit allocation is given in table 143 . remark: only one bit can be set to logic 1 at a time. [1] the reserved bits should always be written with the reset value. table 140. unlock_dev - unlock device register (address 7ch) bit allocation bit 15 14 13 12 11 10 9 8 symbol ulcode[15:8] = aah reset not applicable bus reset not applicable access wwwwwwww bit 7 6 5 4 3 2 1 0 symbol ulcode[7:0] = 37h reset not applicable bus reset not applicable access wwwwwwww table 141. unlock_dev - unlock device register (address 7ch) bit description bit symbol description 15 to 0 ulcode[15:0] unlock code : writing data aa37h unlocks internal registers and fifos for writing, following a resume. table 142. intr_pulse_width - interrupt pulse width register (address 80h) bit description legend: * reset value bit symbol access value description 15 to 0 intr_pulse_ width[15:0 r/w 1eh* interrupt pulse width : the interrupt signal pulse width is configurable while it is in pulse signaling mode. the minimum pulse width is 33.3 ns when this register value is 1. the power-on reset value of 1eh allows a pulse of 1 s to be generated. table 143. test_mode - test mode register (address 84h) bit allocation bit 7 6 5 4 3 2 1 0 symbol forcehs reserved [1] forcefs prbs kstate jstate se0_nak reset 00000000 bus reset 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 107 of 135 isp1763a hi-speed usb otg controller [1] either forcehs or forcefs must be set at a time. [2] of the four bits (prbs, kstate, jstate, and se0_nak), only one bit must be set at a time. table 144. test_mode - test mode register (address 84h) bit description bit symbol description 7 forcehs force high-speed : logic 1 [1] forces the hardware to high-speed mode only and disables the chirp detection logic. 6 to 5 - reserved. 4 forcefs force full-speed : logic 1 [1] forces the physical layer to full-speed mode only and disables the chirp detection logic. 3prbs predetermined random pattern : logic 1 [2] sets the dp and dm pins to toggle in a predetermined random pattern. 2 kstate k state : writing logic 1 [2] sets the dp and dm pins to the k state. 1 jstate j state : writing logic 1 [2] sets the dp and dm pins to the j state. 0 se0_nak se0 nak : writing logic 1 [2] sets the dp and dm pins to a high-speed quiescent state. the device only responds to a valid high-speed in token with a nak.
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 108 of 135 isp1763a hi-speed usb otg controller 12. limiting values 13. recommended operating conditions table 145. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc(i/o) input/output supply voltage ? 0.5 +4.6 v v cc(3v3) supply voltage ? 0.5 +4.6 v v i input voltage on pin x1/clkin ? 0.5 +2.5 v on pins dp1, dm1, dp2, dm2, id ? 0.5 +4.6 v on pins oc1/v bus1 , oc2/v bus2 , psw1_n, psw2_n ? 0.5 +5.5 v other digital i/o pins ? 0.5 v cc(i/o) +0.5 v i lu latch-up current v i < 0 v or v i > v cc(3v3) -100 ma v esd electrostatic discharge voltage i li < 1 a; human body model (jesd22-a114-b) ? 2000 +2000 v i li < 1 a; machine model (jesd22-a115-a) -+200 v t stg storage temperature ? 40 +125 c table 146. recommended operating conditions symbol parameter conditions min typ max unit v cc(i/o) input/output supply voltage v cc(i/o) = 3.3 v 3.0 3.3 3.6 v v cc(i/o) = 1.8 v 1.65 1.8 1.95 v v cc(3v3) supply voltage 3.0 - 3.6 v v i input voltage on pin x1/clkin 0 1.2 1.3 v on pins dp1, dm1, dp2, dm2, id 0 - 3.6 v on pins oc1/v bus1 , oc2/v bus2 , psw1_n, psw2_n 0- 5.25v other digital i/o pins - - v cc(i/o) v t amb ambient temperature ? 40 - +85 c t j junction temperature ? 40 - +125 c
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 109 of 135 isp1763a hi-speed usb otg controller 14. static characteristics [1] when the i/o pins are in definite state. table 147. static characteristics: supply pins v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit i cc(3v3) supply current power-down mode [1] -220 a deep sleep mode - 150 350 a host mode; bus idle - 20 - ma host mode; one port working (high-speed) -36- ma host mode; two ports working (high-speed) -55- ma i cc(i/o) supply current on v cc(i/o) static; no bus activity - - 20 a table 148. static characteristics: digital pins v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit v ih high-level input voltage 0.7v cc(i/o) -- v v il low-level input voltage - - 0.3v cc(i/o) v v hys hysteresis voltage 0.4 - 0.7 v v ol low-level output voltage i ol = 1.5 ma when v cc(i/o) = 1.65 v to 1.95 v --0.4v i ol = 3.0 ma when v cc(i/o) = 3.0 v to 3.6 v --0.4v v oh high-level output voltage i oh = 3.3 ma when v cc(i/o) = 1.65 v to 1.95 v v cc(i/o) ? 0.4 - - v i oh = 6.5 ma when v cc(i/o) = 3.0 v to 3.6 v v cc(i/o) ? 0.4 - - v i li input leakage current v i = 0 v to v cc(i/o) ; push-pull pins --1 a open-drain pins - - 20 a c in input capacitance - - 3 pf table 149. static characteristics: usb interface block (pins dm1, dm2, dp1, dp2) v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit input levels for high-speed v hssq high-speed squelch detection threshold voltage (differential signal amplitude) squelch detected - - 100 mv no squelch detected 150 - - mv v hsdsc high-speed disconnect detection threshold voltage (differential signal amplitude) disconnect detected 625 - - mv disconnect not detected --525mv
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 110 of 135 isp1763a hi-speed usb otg controller [1] the hs termination resistor is disabled, and the pull-up resi stor is connected. only duri ng reset, when both the hub and the device are capable of the high-speed operation. v hscm high-speed data signaling common mode voltage range (guideline for receiver) ? 50 - +500 mv output levels for high-speed v hsoi high-speed idle level voltage ? 10 - +10 mv v hsoh high-speed data signaling high-level voltage 360 - 440 mv v hsol high-speed data signaling low-level voltage ? 10 - +10 mv v chirpj chirp j level (differential voltage) 700 [1] -1100mv v chirpk chirp k level (differential voltage) ? 900 [1] - ? 500 mv input levels for full-speed and low-speed v ih high-level input voltage drive 2.0 - - v v ihz high-level input voltage floating 2.7 - 3.6 v v il low-level input voltage - - 0.8 v v di differential input sensitivity | v dp ? v dm | 0.2 - - v v cm differential common mode voltage range 0.8- 2.5v output levels for full-speed and low-speed v oh high-level output voltage 2.8 - 3.6 v v ol low-level output voltage 0 - 0.3 v v crs output signal crossover voltage 1.3 - 2.0 v impedance z drv driver output impedance includes the r s resistor 40.5 45 49.5 table 149. static characteristics: usb interface block (pins dm1, dm2, dp1, dp2) ?continued v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit table 150. static characteristics: v bus comparators v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit v a_vbus_vld a-device v bus valid voltage - 4.5 - v v a_sess_vld a-device session valid voltage 0.8 1.6 2.0 v v hys(a_sess_vld) a-device session valid hysteresis voltage - 210 - mv v b_sess_vld b-device session valid voltage 2.0 3.6 4.0 v v hys(b_sess_vld) b-device session valid hysteresis voltage - 220 - mv v b_sess_end b-device session end voltage 0.2 0.5 0.8 v v hys(b_sess_end) b-device session end hysteresis voltage - 160 - mv
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 111 of 135 isp1763a hi-speed usb otg controller [1] the v bus input impedance may be lower than 40 k for a short period of time when v bus rises above v cc(3v3) . table 151. static characteristics: v bus resistors v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit r up(vbus) pull-up resistance on pin oc1/v bus1 connect to v cc(3v3) when vbus_chrg = 1 -1.2-k r dn(vbus) pull-down resistance on pin oc1/v bus1 connect to ground when vbus_dischrg = 1 -1.8-k r i(idle)(vbus) idle input resistance on pin oc1/v bus1 40 [1] 65 100 k table 152. static characteristics: id detection circuit v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit v th(id) id detector threshold voltage 1.0 - 2.0 v r up(id) id pull-up resistance bit id_pullup = 1 - 20 - k
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 112 of 135 isp1763a hi-speed usb otg controller 15. dynamic characteristics [1] recommended accuracy of the clock frequency is 50 ppm for the crystal and the oscillator. table 153. dynamic characteristics: system clock v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit crystal oscillator f clk clock frequency freqsel2 = 0, freqsel1 = 0 [1] -12-mhz freqsel2 = 0, freqsel1 = 1 [1] -19.2-mhz freqsel2 = 1, freqsel1 = 0 [1] -24-mhz external clock input j external clock jitter - - 500 ps clock duty cycle - 50 - % v i(x1/clkin) input voltage on pin x1/clkin - 1.2 - v t r rise time - - 3 ns t f fall time - - 3 ns table 154. dynamic characteristics: power-up and reset v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit t dmy_rd(reset_n) active-low reset to dummy read operation regulator filter capacitor c reg(1v2) =4.7 f 10 - ms t dmy_rd(reset) active-high reset to dummy read operation regulator filter capacitor c reg(1v2) =4.7 f 0- - ns t opr_rd(dmy_rd) dummy read to first valid read operation regulator filter capacitor c reg(1v2) =4.7 f 10 - - ms table 155. dynamic characteristics: digital pins v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit sr slew rate standard load (rise, fall) 1 - 4 v/ns table 156. dynamic characteristics: high-speed source electrical v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit driver characteristics t hsr rise time (10% to 90%) 500 - - ps t hsf fall time (10% to 90%) 500 - - ps
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 113 of 135 isp1763a hi-speed usb otg controller clock timing t hsdrat high-speed data rate 479.76 - 480.24 mbit/s t hsfram microframe interval 124.9375 - 125.0625 s t hsrfi consecutive microframe interval difference 1 - four high-speed bit times ns table 156. dynamic characteristics: high-speed source electrical ?continued v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit table 157. dynamic characteristics: full-speed source electrical v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit driver characteristics t fr rise time c l = 50 pf; 10% to 90% of | v oh ? v ol | 4- 20ns t ff fall time c l = 50 pf; 90% to 10% of | v oh ? v ol | 4- 20ns t frfm differential rise and fall time matching 90 - 111.1 % data timing: see figure 9 t fdeop source jitter for differential transition to se0 transition full-speed timing ? 2- +5ns t feopt source se0 interval of eop 160 - 175 ns t feopr receiver se0 interval of eop 82 - - ns t ldeop upstream facing port source jitter for differential transition to se0 transition low-speed timing ? 40 - +100 ns t leopt source se0 interval of eop 1.25 - 1.5 s t leopr receiver se0 interval of eop 670 - - ns t fst width of se0 interval during differential transition --14ns table 158. dynamic characteristics: low-speed source electrical v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter conditions min typ max unit driver characteristics t lr transition time: rise time 75 - 300 ns t lf transition time: fall time 75 - 300 ns t lrfm rise and fall time matching 90 - 125 %
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 114 of 135 isp1763a hi-speed usb otg controller t period is the bit duration corresponding to the usb data rate. fig 9. usb source differential data-to-eop transition skew and eop width 004aaa9 29 t period differential data lines crossover point differential data to se0/eop skew n t period + t fdeop n t period + t ldeop source eop width: t feopt , t leopt receiver eop width: t feopr , t leop r crossover point extended + 3.3 v 0 v
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 115 of 135 isp1763a hi-speed usb otg controller 15.1 timing 15.1.1 dma dreq is continuously asserted until the last transfer is done or the fifo is full or empty. data strobes: read and write. (1) programmable polarity: shown as active low. (2) programmable polarity: shown as active high. (3) in single cycle mode, n = 1, read or write only asserts one time when dreq asserts. fig 10. dma read and write t h19 t w19 t su19 t d19 t su29 t d29 t h29 t cy19 (write) ad[15:0] (read) ad[15:0] dreq (2) dack (1) r d_n/ds_n/re_n/oe_n 004aab03 4 t su39 t w29 t a19 t h39 ad1 ad2 adn (3) ad1 ad2 adn (3) t cy29 wr_n/rw_n/we_n or table 159. dma timing v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter description host dma peripheral dma unit min max min max t su19 dreq set-up time before dack assertion 0 - 0 - ns t d19 dack deassertion to next dreq assertion time 56 - 82 - ns t h19 dreq hold time after last strobe assertion 0 53 0 53 ns t w19 rd_n/ds_n/re_n/oe_n or wr_n/rw_n/we_n pulse width 25 - 40 - ns t w29 rd_n/ds_n/re_n/oe_n or wr_n/rw_n/we_n recovery time 21 - 35 - ns t d29 data valid time after rd_n/ds_n/re_n/oe_n assertion -30- 30ns t h29 read data hold time after rd_n/ds_n/re_n/oe_n deassertion 2102 10ns t h39 write data hold time after wr_n/rw_n/we_n deassertion 0- 0 -ns t su29 write data set-up time before wr_n/rw_n/we_n deassertion 10 - 10 - ns
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 116 of 135 isp1763a hi-speed usb otg controller 15.1.2 pio t su39 dack set-up time before rd_n/ds_n/re_n/oe_n or wr_n/rw_n/we_n assertion 0- 0 - ns t a19 dack deassertion after rd_n/ds_n/re_n/oe_n or wr_n/rw_n/we_n deassertion 0- 0 -ns t cy19 dma read/write cycle time 51 - 75 - ns t cy29 dma request cycle time 104 - 104 - ns table 159. dma timing ?continued v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v or 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter description host dma peripheral dma unit min max min max table 160. pio timing v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter description condition sram mode multiplex mode unit min max min max t cs cs_n/ce_n set-up time before wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low 0- 0-ns t ch cs_n/ce_n hold time after wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n high 0- 0-ns t cp cs_n/ce_n pulse width for read 30 - 30 - ns cs_n/ce_n pulse width for write 17 - 17 - ns t csadval cs_n/ce_n set-up time before address latch -- 6-ns t asrw address set-up time before wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low 0- --ns t ahrw address hold time after wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low 10 - - - ns t ah address hold time after address latch - - 0 - ns t as address set-up time before address latch - - 10 - ns t ap address latch pulse width - - 17 - ns t wc write cycle time host or otg 38 - 68 ns peripheral 100 - 100 ns t wp wr_n/rw_n/we_n pulse width 17 - 17 - ns t dh rd_n/ds_n/re_n/oe_n high to output hi-z 1 10 1 10 ns wr_n/rw_n/we_n high to input hi-z 0 - 0 - ns t dadvh data set-up time before data latch 10 - 10 - ns t oe rd_n/ds_n/re_n/oe_n low to data output enable 2- 2-ns t bds ready to wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low -- 5-ns
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 117 of 135 isp1763a hi-speed usb otg controller t rp rd_n/ds_n/re_n/oe_n pulse width 30 - 30 - ns t rc rd_n/ds_n/re_n/oe_n cycle time host or otg 49 - 68 - ns peripheral 100 - 100 - ns t p13 memory read pre-fetch time 105 - 105 - ns table 160. pio timing ?continued v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =3.3v; t amb = +25 c; unless otherwise specified. symbol parameter description condition sram mode multiplex mode unit min max min max table 161. pio timing v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =1.8v; t amb = +25 c; unless otherwise specified. symbol parameter description conditions sram mode multiplex mode unit min max min max t cs cs_n/ce_n set-up time before wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low 0-0-ns t ch cs_n/ce_n hold time after wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n high 0-0-ns t cp cs_n/ce_n pulse width for read 38 - 38 - ns cs_n/ce_n pulse width for write 17 - 17 - ns t csadval cs_n/ce_n set-up time before address latch --6-ns t asrw address set-up time before wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low 0-- -ns t ahrw address hold time after wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low 10 - - - ns t ah address hold time after address latch --0-ns t as address set-up time before address latch --10-ns t ap address latch pulse width - - 17 - ns t wc write cycle time host or otg 38 - 68 ns peripheral 100 - 100 ns t wp wr_n/rw_n/we_n pulse width 17 - 17 - ns t dh rd_n/ds_n/re_n/oe_n high to output hi-z 110110ns wr_n/rw_n/we_n high to input hi-z 0-0-ns t dadvh data set-up time before data latch 10 - 10 - ns t oe rd_n/ds_n/re_n/oe_n low to data output enable 2-2-ns t bds ready to wr_n/rw_n/we_n or rd_n/ds_n/re_n/oe_n low --5-ns
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 118 of 135 isp1763a hi-speed usb otg controller t rp rd_n/ds_n/re_n/oe_n pulse width 38 - 38 - ns t rc rd_n/ds_n/re_n/oe_n cycle time host or otg 54 - 68 - ns peripheral 100 - 100 - ns t p13 memory read pre-fetch time 113 - 113 - ns table 161. pio timing ?continued v cc(3v3) = 3.0 v to 3.6 v; v cc(i/o) = 1.65 v to 1.95 v; t amb = ? 40 c to +85 c; unless otherwise specified. typical case refers to v cc(3v3) =3.3v, v cc(i/o) =1.8v; t amb = +25 c; unless otherwise specified. symbol parameter description conditions sram mode multiplex mode unit min max min max fig 11. read in sram mode 004aab02 5 ad[15:0] a[7:0] ale/adv_n cle rd_n/ds_n/ re_n/oe_n cs_n/ce_n w r_n/rw_n/ we_n t oe t dh data address t ahrw t asrw t rp t ch t cs t cp t rc
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 119 of 135 isp1763a hi-speed usb otg controller fig 12. write in sram mode 004aab026 ad[15:0] a[7:0] ale/adv_n cle w r_n/rw_n/we_n cs_n/ce_n rd_n/ds_n/ re_n/oe_n t dadvh t dh data address t ahrw t asrw t wp t ch t cs t cp t wc
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 120 of 135 isp1763a hi-speed usb otg controller fig 13. read in proprietary sram mode 004ab0 5 ad[15:0] a[7:0] ale/adv_n cle rd_n/ds_n/ re_n/oe_n cs_n/ce_n w r_n/rw_n/ we_n t oe t dh data address t ahrw t asrw t rp t ch t cs t cp t rc
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 121 of 135 isp1763a hi-speed usb otg controller fig 14. write in proprietary sram mode 004ab06 ad[15:0] a[7:0] ale/adv_n cle rd_n/ds_n/ re_n/oe_n cs_n/ce_n w r_n/rw_n/ we_n t dadvh t dh data address t ahrw t asrw t wp t ch t cs t cp t wc fig 15. read in multiplex nand mode data t as address t ah t bds t dh t as command t ah ad[15:0] t oe ale/ adv_n cle cs_n/ce_n t csadval t cs t rc rd_n/ds_n/ re_n/oe_n 004aab027 w r_n/rw_n/ we_n t cs t ah t ah t rp t bds t as t as t wp t wp t cp t ch
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 122 of 135 isp1763a hi-speed usb otg controller fig 16. write in multiplex nand mode data t as address t ah t bds t dh t as command t ah ad[15:0] ale/ adv_n t ah t dadvh cle t ah rd_n/ds_n/ re_n/oe_n cs_n/ce_n 004aab028 w r_n/rw_n/ we_n t csadval t bds t cs t ch t cp t cs t wp t as t as t wp t wp t wc fig 17. read in general multiplex mode 004aab030 ad[15:0] data t as address ale/ adv_n cle rd_n/ds_n/ re_n/oe_n cs_n/ce_n w r_n/rw_n/ we_n t ah t bds t dh t csadval t oe t ap t rp t ch t rc
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 123 of 135 isp1763a hi-speed usb otg controller fig 18. write in general multiplex mode 004aab029 ad[15:0] data t as address ale/ adv_n cle rd_n/ds_n/ re_n/oe_n cs_n/ce_n w r_n/rw_n/ we_n t ah t bds t dh t csadval t ch t dadvh t ap t wp t wc fig 19. read in multiplex nor mode 004aab03 2 ad[15:0] data valid t as address ale/ adv_n cle rd_n/ds_n/ re_n/oe_n cs_n/ce_n w r_n/rw_n/ we_n t ah t bds t dh t csadval t oe t ap t rp t ch t rc
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 124 of 135 isp1763a hi-speed usb otg controller fig 20. write in multiplex nor mode 004aab03 1 ad[15:0] data t as address ale/ adv_n cle rd_n/ds_n/ re_n/oe_n cs_n/ce_n w r_n/rw_n/ we_n t ah t bds t dh t csadval t dadvh t ap t ch t wp t wc fig 21. memory read prefetch 004aab033 ad[15:0] rd_n/ds_n/ re_n/oe_n w r_n/rw_n/ we_n t p13
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 125 of 135 isp1763a hi-speed usb otg controller 16. package outline fig 22. package outline vfqfpn64 references outline version european projection issue date iec jedec jeita --- - - - - - - - - - notes 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. 2. mold flash on exposed inner terminal is allowed. unit mm max nom min 1.00 0.90 0.85 0.05 0.02 0.00 0.2 9.1 9.0 8.9 3.95 3.80 3.65 6.2 6.1 6.0 6.9 6.8 6.7 9.1 9.0 8.9 6.2 6.1 6.0 0.5 7.5 a dimensions (mm are the original dimensions) vfqfpn64: plastic thermal enhanced very thin quad flat package; no leads; 6 4 terminals; body 9 x 9 x 1.0 mm 0 5 10 mm scale a 1 b 0.30 0.21 0.18 c d (1) d h d j d k 6.6 6.5 6.4 d m e (1) e h 3.95 3.80 3.65 e j e k 6.6 6.5 6.4 e m 6.9 6.8 6.7 e n 7.7 7.6 7.5 d n 7.7 7.6 7.5 e e 1 e 2 7.5 0.05 0.05 l 0.5 0.4 0.3 v 0.1 w yy 1 0.1 terminal 1 index area b a d e c y c y 1 x detail x a c a 1 b e 2 e 1 e e 1/2 e 1/2 e a c b v m c w m terminal 1 index area d h e h l e j e k e m e n d j d k d m d n 16 1 33 48 32 49 64 17 08-03-10 08-03-26
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 126 of 135 isp1763a hi-speed usb otg controller fig 23. package outline tfbga64 references outline version european projection issue date iec jedec jeita - - - - - - - - - 06-09-22 06-09-27 unit a max mm 1.1 0.25 0.15 0.85 0.75 4.1 3.9 4.1 3.9 0.4 2.8 0.15 0.05 0.1 a 1 dimensions (mm are the original dimensions) t fbga64: plastic thin fine-pitch ball grid array package; 64 balls; body 4 x 4 x 0.8 mm 0 2.5 5 mm scale a 2 b 0.3 0.2 d e e e 1 e 2 2.8 v w y 0.08 y 1 b a ball a1 index area d e e 2 e 1/2 e b e 1 e 1/2 e a c b ? v m c ? w m a b c d e f h g 2468 1357 ball a1 index area c y c y 1 x detail x a a 1 a 2 - - -
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 127 of 135 isp1763a hi-speed usb otg controller 17. abbreviations 18. references [1] universal serial bus specification rev. 2.0 [2] enhanced host controller interface specification for universal serial bus rev. 1.0 [3] on-the-go supplement to the usb specification rev. 1.3 table 162. abbreviations acronym description ack acknowledge atl asynchronous transfer list atx analog usb transceiver dma direct memory access ehci enhanced host controller interface fifo first in, first out hc host controller hnp host negotiation protocol hs high-speed int interrupt iso isochronous nak not acknowledge ohci open host controller interface otg on-the-go pcb printed-circuit board pci peripheral component interconnect pid packet identifier pio parallel i/o pll phase-locked loop ptd proprietary transfer descriptor sie serial interface engine sof start-of-frame srp session request protocol tt transaction translator usb universal serial bus
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 128 of 135 isp1763a hi-speed usb otg controller 19. revision history table 163. revision history revision release date data sheet status change notice 4 14-oct-2013 product data sheet - modifications: publication of the features and description on the web product page. no change in the content. 3 23-sep-2013 product data sheet - modifications: re-branding to st. no change in the content. 2 24-feb-2011 product data sheet - modifications: ? table 153 ? dynamic characteristics: system clock ? : updated conditions for f clk . 1 18-mar-2010 product data sheet -
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 129 of 135 continued >> isp1763a hi-speed usb otg controller 20. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. bus configuration modes . . . . . . . . . . . . . . . . . 11 table 5. pinning information of the bus interface . . . . .12 table 6. register address . . . . . . . . . . . . . . . . . . . . . . .15 table 7. memory address . . . . . . . . . . . . . . . . . . . . . . .21 table 8. using the irq mask and or irq mask or registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 9. endpoint access and programmability . . . . . . .26 table 10. power supply . . . . . . . . . . . . . . . . . . . . . . . . . .28 table 11. overview of otg controller-specific registers .30 table 12. otg_ctrl - otg control register (address set: e4h, clear: e6h) bit allocation . . . . . . . . . . . . .30 table 13. otg_ctrl - otg control register (address set: e4h, clear: e6h) bit description . . . . . . . . . . . .31 table 14. otg_intr_src - otg interrupt source register (address e8h) bit allocation . . . . . . . . . . . . . . .32 table 15. otg_intr_src - otg interrupt source register (address e8h) bit description . . . . . . . . . . . . . .32 table 16. otg_intr_l - otg interrupt latch register (address set: ech, clear: eeh) bit allocation . .32 table 17. otg_intr_l - otg interrupt latch register (address set: ech, clear: eeh) bit description .33 table 18. otg_intr_en_f - otg interrupt enable fall register (address set: f0h, clear: f2h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 19. otg_intr_en_f - otg interrupt enable fall register (address set: f0h, clear: f2h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 20. otg_intr_en_r - otg interrupt enable rise register (address set: f4h, clear: f6h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 21. otg_intr_en_r - otg interrupt enable rise register (address set: f4h, clear: f6h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 22. otg_tmr - otg timer register (address low word set: f8h, low word clear: fah; high word set: fch, high word clear: feh) bit allocation . . . . .35 table 23. otg_tmr - otg timer register (address low word set: f8h, low word clear: fah; high word set: fch, high word clear: feh) bit description . . . .35 table 24. overview of host controller-specific registers .36 table 25. usbcmd - usb command register (address 8ch) bit allocation . . . . . . . . . . . . . . . . . . . . . .37 table 26. usbcmd - usb command register (address 8ch) bit description . . . . . . . . . . . . . . . . . . . . .37 table 27. usbsts - usb status register (address 90h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 28. usbsts - usb status register (address 90h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 29. usbintr - usb interrupt register (address 94h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 30. usbintr - usb interrupt register (address 94h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 31. frindex - frame index register (address: 98h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 32. frindex - frame index register (address: 98h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 33. configflag - configure flag register (address 9ch) bit allocation . . . . . . . . . . . . . . . . . . . . . . 40 table 34. configflag - configure flag register (address 9ch) bit description . . . . . . . . . . . . . . . . . . . . . 41 table 35. portsc1 - port status and control 1 register (address a0h) bit allocation . . . . . . . . . . . . . . 41 table 36. portsc1 - port status and control 1 register (address a0h) bit description . . . . . . . . . . . . . 41 table 37. iso ptd done map register (address a4h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 38. iso ptd skip map register (address a6h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 39. iso ptd last ptd register (address a8h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 40. int ptd done map register (address aah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 41. int ptd skip map register (address ach) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 42. int ptd last ptd register (address aeh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 43. atl ptd done map register (address b0h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 44. atl ptd skip map register (address b2h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 45. atl ptd last ptd register (address b4h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 46. hw mode control - hardware mode control register (address b6h) bit allocation . . . . . . . . 45 table 47. hw mode control - hardware mode control register (address b6h) bit description . . . . . . . 45 table 48. sw reset - software reset register (address b8h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 46 table 49. sw reset - software reset register (address b8h) bit description . . . . . . . . . . . . . . . . . . . . . 47 table 50. hcbufferstatus - host controller buffer status register (address bah) bit allocation . . . . . . . . 47 table 51. hcbufferstatus - host controller buffer status
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 130 of 135 isp1763a hi-speed usb otg controller register (address bah) bit description . . . . . . .48 table 52. hcdmaconfiguration - host controller direct memory access configuration register (address bch) bit allocation . . . . . . . . . . . . . . . . . . . . . .48 table 53. hcdmaconfiguration - host controller direct memory access configuration register (address bch) bit description . . . . . . . . . . . . . . . . . . . . .49 table 54. atl done timeout register (address: c0h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 table 55. memory register (address c4h) bit allocation .50 table 56. memory register (address c4h) bit description 50 table 57. data port register (address: c6h) bit description . 50 table 58. edge interrupt count register (address c8h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 59. edge interrupt count register (address c8h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 60. dma data port register (address 60h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 61. dma start address register (address cch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 62. power down control register (address d0h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 table 63. power down control register (address d0h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 64. hcinterrupt - host controller interrupt register (address d4h) bit description . . . . . . . . . . . . . .53 table 65. hcinterrupt - host controller interrupt register (address d4h) bit description . . . . . . . . . . . . . .54 table 66. hcinterruptenable - host controller interrupt enable register (address d6h) bit allocation . .55 table 67. hcinterruptenable - host controller interrupt enable register (address d6h) bit description .56 table 68. iso irq mask or register (address d8h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 69. int irq mask or register (address dah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 70. atl irq mask or register (address dch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 71. iso irq mask and register (address deh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 table 72. int irq mask and register (address e0h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 73. atl irq mask and register (address e2h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 table 74. high-speed bulk in and out: bit allocation . . .60 table 75. high-speed bulk in and out: bit description . .61 table 76. high-speed isochronous in and out: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 table 77. high-speed isochronous in and out: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 78. high-speed interrupt in and out: bit allocation . 68 table 79. high-speed interrupt in and out: bit description 69 table 80. microframe description . . . . . . . . . . . . . . . . . .71 table 81. start and complete split for bulk: bit allocation .72 table 82. start and complete split for bulk: bit description . 73 table 83. se description . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 84. start and complete split for isochronous: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 85. start and complete split for isochronous: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 86. start and complete split for interrupt: bit allocation 80 table 87. start and complete split for interrupt: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 88. microframe description . . . . . . . . . . . . . . . . . . 83 table 89. se description . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 90. peripheral controller-specific register overview 84 table 91. addr - address register (address 00h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 92. addr - address register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 93. mode - mode register (address 0ch) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 94. mode - mode register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 95. intr_conf - interrupt configuration register (address 10h) bit allocation . . . . . . . . . . . . . . . 87 table 96. intr_conf - interrupt configuration register (address 10h) bit description . . . . . . . . . . . . . . 87 table 97. debug mode settings . . . . . . . . . . . . . . . . . . . 87 table 98. dcinterruptenable - device controller interrupt enable register (address 14h) bit allocation . . 88 table 99. dcinterruptenable - device controller interrupt enable register (address 14h) bit description . 88 table 100.endp_index - endpoint index register (address 2ch) bit allocation . . . . . . . . . . . . . . . . . . . . . . 90 table 101. endp_index - endpoint index register (address 2ch) bit description . . . . . . . . . . . . . . . . . . . . . 90 table 102.addressing of endpoint buffers . . . . . . . . . . . . 90 table 103.ctrl_func- control function register (address 28h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 90 table 104. ctrl_func- control function register (address 28h) bit description . . . . . . . . . . . . . . . . . . . . . 91 table 105.data_port - data port register (address 20h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 106.buffer_length - buffer length register (address 1ch) bit description . . . . . . . . . . . . . 92 table 107.dcbufferstatus - device controller buffer status register (address 1eh) bit allocation . . . . . . . . 93 table 108.dcbufferstatus - device controller buffer status register (address 1eh) bit description . . . . . . . 93 table 109.endp_maxpktsize - endpoint maxpacketsize register (address 04h) bit allocation . . . . . . . . 93 table 110. endp_maxpktsize - endpoint maxpacketsize register (address 04h) bit description . . . . . . . 94 table 111. endp_type - endpoint type register (address 08h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 94 table 112. endp_type - endpoint type register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . 95 table 113. control bits for gdma read/write (opcode = 00h/01h) . . . . . . . . . . . . . . . . . . . . . 96 table 114. dma_cmd - dma command register (address
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 131 of 135 isp1763a hi-speed usb otg controller 30h) bit allocation . . . . . . . . . . . . . . . . . . . . . .96 table 115. dma_cmd - dma command register (address 30h) bit description . . . . . . . . . . . . . . . . . . . . .96 table 116. dma commands . . . . . . . . . . . . . . . . . . . . . . .96 table 117. dma_xfr_ctr - dma transfer counter register (address 34h) bit allocation . . . . . . . . . . . . . . .97 table 118. dma_xfr_ctr - dma transfer counter register (address 34h) bit description . . . . . . . . . . . . . .98 table 119. dcdmaconfiguration - device controller direct memory access configuration register (address 38h) bit allocation . . . . . . . . . . . . . . . . . . . . . .98 table 120.dcdmaconfiguration - device controller direct memory access configuration register (address 38h) bit description . . . . . . . . . . . . . . . . . . . . .98 table 121.dma_hw - dma hardware register (address 3ch) bit allocation . . . . . . . . . . . . . . . . . . . . . .99 table 122.dma_hw - dma hardware register (address 3ch) bit description . . . . . . . . . . . . . . . . . . . . .99 table 123.dma_intr_reason - dma interrupt reason register (address 50h) bit allocation . . . . . . . . .99 table 124.dma_intr_reason - dma interrupt reason register (address 50h) bit description . . . . . .100 table 125.internal eot-functional relation with bit dma_xfer_ok . . . . . . . . . . . . . . . . . . . . . .100 table 126. status of the bits in the dma interrupt reason register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 table 127.dma_intr_en - dma interrupt enable register (address 54h) bit allocation . . . . . . . . . . . . . .101 table 128.dma_intr_en - dma interrupt enable register (address 54h) bit description . . . . . . . . . . . . .101 table 129.dma_endp - dma endpoint register (address 58h) bit allocation . . . . . . . . . . . . . . . . . . . . .101 table 130.dma_endp - dma endpoint register (address 58h) bit description . . . . . . . . . . . . . . . . . . . .102 table 131.dma_brst_ctr - dma burst counter register (address 64h) bit allocation . . . . . . . . . . . . . .102 table 132.dma_brst_ctr - dma burst counter register (address 64h) bit description . . . . . . . . . . . . .102 table 133.dcinterrupt - device controller interrupt register (address 18h) bit allocation . . . . . . . . . . . . . .103 table 134.dcinterrupt - device controller interrupt register (address 18h) bit description . . . . . . . . . . . . .103 table 135.dcchipid - device controller chip identifier register (address 70h) bit description . . . . . .104 table 136.frame_no - frame number register (address 74h) bit allocation . . . . . . . . . . . . . . . . . . . . .105 table 137. frame_no - frame number register (address 74h) bit description . . . . . . . . . . . . . . . . . . . .105 table 138.scratch - scratch register (address 78h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 table 139.scratch - scratch register (address 78h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .105 table 140.unlock_dev - unlock device register (address 7ch) bit allocation . . . . . . . . . . . . . . . . . . . . .106 table 141.unlock_dev - unlock device register (address 7ch) bit description . . . . . . . . . . . . . . . . . . . .106 table 142.intr_pulse_width - interrupt pulse width register (address 80h) bit description . . . . . .106 table 143.test_mode - test mode register (address 84h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 144.test_mode - test mode register (address 84h) bit description . . . . . . . . . . . . . . . . . . . . . . . . 107 table 145.limiting values . . . . . . . . . . . . . . . . . . . . . . . 108 table 146.recommended operating conditions . . . . . . 108 table 147.static characteristics: supply pins . . . . . . . . . 109 table 148.static characteristics: digital pins . . . . . . . . . 109 table 149.static characteristics: usb interface block (pins dm1, dm2, dp1, dp2) . . . . . . . . . . . . . . . . . 109 table 150.static characteristics: v bus comparators . . . 110 table 151.static characteristics: v bus resistors . . . . . . . 111 table 152.static characteristics: id detection circuit . . . 111 table 153.dynamic characteristics: system clock . . . . . 112 table 154.dynamic characteristics: power-up and reset 112 table 155.dynamic characteristics: digital pins . . . . . . . 112 table 156.dynamic characteristics: high-speed source electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 157.dynamic characteristics: full-speed source electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 158.dynamic characteristics: low-speed source electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 159.dma timing . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 160.pio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 161.pio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 162.abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 163.revision history . . . . . . . . . . . . . . . . . . . . . . . 128
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 132 of 135 continued >> isp1763a hi-speed usb otg controller 21. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 2. pin configuration tfbga64 . . . . . . . . . . . . . . . . . .5 fig 3. pin configuration vfqfpn64 . . . . . . . . . . . . . . . .6 fig 4. write operation. . . . . . . . . . . . . . . . . . . . . . . . . . .13 fig 5. hnp sequence of events . . . . . . . . . . . . . . . . . . .18 fig 6. internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 fig 7. memory segmentation and access block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 fig 8. power-up and reset sequence . . . . . . . . . . . . . . .29 fig 9. usb source differential data-to-eop transition skew and eop width . . . . . . . . . . . . . . . . . . . . . . . . . . 114 fig 10. dma read and write . . . . . . . . . . . . . . . . . . . . . . 115 fig 11. read in sram mode . . . . . . . . . . . . . . . . . . . . . 118 fig 12. write in sram mode . . . . . . . . . . . . . . . . . . . . . 119 fig 13. read in proprietary sram mode . . . . . . . . . . . .120 fig 14. write in proprietary sram mode . . . . . . . . . . . .121 fig 15. read in multiplex nand mode . . . . . . . . . . . . .121 fig 16. write in multiplex nand mode . . . . . . . . . . . . .122 fig 17. read in general multiplex mode . . . . . . . . . . . .122 fig 18. write in general multiplex mode. . . . . . . . . . . . .123 fig 19. read in multiplex nor mode . . . . . . . . . . . . . .123 fig 20. write in multiplex nor mode. . . . . . . . . . . . . . .124 fig 21. memory read prefetch . . . . . . . . . . . . . . . . . . . .124 fig 22. package outline vfqfpn64 . . . . . . . . . . . . . . .125 fig 23. package outline tfbga64 . . . . . . . . . . . . . . . .126
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 133 of 135 isp1763a hi-speed usb otg controller 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 host or peripheral roles . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . 11 8.1 cpu bus interface . . . . . . . . . . . . . . . . . . . . . 11 8.2 interface mode lock . . . . . . . . . . . . . . . . . . . . 12 8.3 sram bus interface mode . . . . . . . . . . . . . . . 12 8.4 nand bus interface mode . . . . . . . . . . . . . . . 13 8.5 nor bus interface mode . . . . . . . . . . . . . . . . 13 8.6 general multiplex bus interface mode . . . . . . 14 8.7 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 14 8.8 on-the-go (otg) controller. . . . . . . . . . . . . . 16 8.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.8.2 dual-role device . . . . . . . . . . . . . . . . . . . . . . . 16 8.8.3 session request protocol (srp) . . . . . . . . . . 17 8.8.3.1 b-device initiating srp . . . . . . . . . . . . . . . . . . 17 8.8.3.2 a-device responding to srp . . . . . . . . . . . . . 17 8.8.4 host negotiation protocol (hnp) . . . . . . . . . . 17 8.8.4.1 sequence of hnp events . . . . . . . . . . . . . . . . 18 8.8.5 power saving in the idle state and during wake-up 19 8.9 usb host controller. . . . . . . . . . . . . . . . . . . . . 19 8.9.1 isp1763a usb host controller and hub internal architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.9.2 host controller buffer memory block . . . . . . . . 20 8.9.2.1 general considerations. . . . . . . . . . . . . . . . . . 20 8.9.2.2 structure of the host controller memory . . . . . 20 8.9.3 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.10 usb peripheral controller . . . . . . . . . . . . . . . . 24 8.10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.10.2 peripheral controller data transfer operation . 25 8.10.2.1 in data transfer . . . . . . . . . . . . . . . . . . . . . . . . 25 8.10.2.2 out data transfer . . . . . . . . . . . . . . . . . . . . . . 25 8.10.3 endpoint description . . . . . . . . . . . . . . . . . . . . 25 8.10.4 peripheral controller suspend . . . . . . . . . . . . . 26 8.10.5 peripheral controller resume. . . . . . . . . . . . . . 27 8.10.6 remote wake-up . . . . . . . . . . . . . . . . . . . . . . 27 8.11 phase-locked loop (pll) clock multiplier . . . 27 8.12 power management . . . . . . . . . . . . . . . . . . . . 27 8.12.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.12.2 power modes . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.2.1 operation mode . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.2.2 suspend mode . . . . . . . . . . . . . . . . . . . . . . . . 28 8.12.2.3 deep sleep mode . . . . . . . . . . . . . . . . . . . . . . 28 8.12.2.4 power-down mode . . . . . . . . . . . . . . . . . . . . . 28 8.12.2.5 isp1763a wake up . . . . . . . . . . . . . . . . . . . . . 28 8.12.2.6 isolation mode . . . . . . . . . . . . . . . . . . . . . . . . 29 8.12.3 power-up and reset sequence . . . . . . . . . . . . 29 8.12.4 atx reference voltage . . . . . . . . . . . . . . . . . . 29 9 otg controller-specific registers . . . . . . . . . 30 9.1 otg control register . . . . . . . . . . . . . . . . . . . 30 9.1.1 otg control register . . . . . . . . . . . . . . . . . . . 30 9.2 otg interrupt registers . . . . . . . . . . . . . . . . . 31 9.2.1 otg interrupt source register . . . . . . . . . . . . 31 9.2.2 otg interrupt latch register . . . . . . . . . . . . . 32 9.2.3 otg interrupt enable fall register. . . . . . . . . 33 9.2.4 otg interrupt enable rise register . . . . . . . . 34 9.3 otg timer register . . . . . . . . . . . . . . . . . . . . 35 9.3.1 otg timer register . . . . . . . . . . . . . . . . . . . . 35 10 host controller-specific registers . . . . . . . . . 36 10.1 ehci operational registers. . . . . . . . . . . . . . . 37 10.1.1 usbcmd register . . . . . . . . . . . . . . . . . . . . . 37 10.1.2 usbsts register . . . . . . . . . . . . . . . . . . . . . . 37 10.1.3 usbintr register . . . . . . . . . . . . . . . . . . . . . 38 10.1.4 frindex register . . . . . . . . . . . . . . . . . . . . . 39 10.1.5 configflag register. . . . . . . . . . . . . . . . . . 40 10.1.6 portsc1 register . . . . . . . . . . . . . . . . . . . . . 41 10.1.7 iso ptd done map register . . . . . . . . . . . . . 42 10.1.8 iso ptd skip map register . . . . . . . . . . . . . . 42 10.1.9 iso ptd last ptd register . . . . . . . . . . . . . . 43 10.1.10 int ptd done map register . . . . . . . . . . . . . 43 10.1.11 int ptd skip map register . . . . . . . . . . . . . . 43 10.1.12 int ptd last ptd register . . . . . . . . . . . . . . 43 10.1.13 atl ptd done map register . . . . . . . . . . . . . 44 10.1.14 atl ptd skip map register . . . . . . . . . . . . . . 44 10.1.15 atl ptd last ptd register . . . . . . . . . . . . . . 44 10.2 configuration registers. . . . . . . . . . . . . . . . . . 45 10.2.1 hw mode control register . . . . . . . . . . . . . . . 45 10.2.2 sw reset register . . . . . . . . . . . . . . . . . . . . . 46 10.2.3 hcbufferstatus register . . . . . . . . . . . . . . . . . 47 10.2.4 hcdmaconfiguration register . . . . . . . . . . . . 48 10.2.5 atl done timeout register . . . . . . . . . . . . . . 49 10.2.6 memory register . . . . . . . . . . . . . . . . . . . . . . . 49 10.2.7 data port register . . . . . . . . . . . . . . . . . . . . . . 50 10.2.8 edge interrupt count register. . . . . . . . . . . . . 50 10.2.9 dma data port register . . . . . . . . . . . . . . . . . 51 10.2.10 dma start address register . . . . . . . . . . . . . . 51 10.2.11 power down control register . . . . . . . . . . . . . 51 10.3 interrupt registers. . . . . . . . . . . . . . . . . . . . . . 53 10.3.1 hcinterrupt register . . . . . . . . . . . . . . . . . . . . 53 10.3.2 hcinterruptenable register . . . . . . . . . . . . . . . 55 10.3.3 iso irq mask or register. . . . . . . . . . . . . . 57 10.3.4 int irq mask or register . . . . . . . . . . . . . . 57 10.3.5 atl irq mask or register. . . . . . . . . . . . . . 57 10.3.6 iso irq mask and register. . . . . . . . . . . . . 57 10.3.7 int irq mask and register . . . . . . . . . . . . . 58 10.3.8 atl irq mask and register. . . . . . . . . . . . . 58 10.4 proprietary transfer descriptor (ptd) . . . . . . 58 10.4.1 high-speed bulk in and out. . . . . . . . . . . . . 60 10.4.2 high-speed isochronous in and out . . . . . . 64 10.4.3 high-speed interrupt in and out . . . . . . . . . 68 10.4.4 start and complete split for bulk. . . . . . . . . . . 72
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 134 of 135 isp1763a hi-speed usb otg controller 10.4.5 start and complete split for isochronous. . . . . 76 10.4.6 start and complete split for interrupt . . . . . . . . 80 11 peripheral controller-specific registers . . . . . 84 11.1 register access . . . . . . . . . . . . . . . . . . . . . . . 84 11.2 initialization registers . . . . . . . . . . . . . . . . . . . 85 11.2.1 address register . . . . . . . . . . . . . . . . . . . . . . . 85 11.2.2 mode register . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.2.3 interrupt configuration register . . . . . . . . . . . . 86 11.2.4 dcinterruptenable register . . . . . . . . . . . . . . . 87 11.3 data flow registers . . . . . . . . . . . . . . . . . . . . . 89 11.3.1 endpoint index register. . . . . . . . . . . . . . . . . . 89 11.3.2 control function register . . . . . . . . . . . . . . . . 90 11.3.3 data port register . . . . . . . . . . . . . . . . . . . . . . 91 11.3.4 buffer length register . . . . . . . . . . . . . . . . . . . 92 11.3.5 dcbufferstatus register. . . . . . . . . . . . . . . . . . 93 11.3.6 endpoint maxpacketsize register. . . . . . . . . . 93 11.3.7 endpoint type register . . . . . . . . . . . . . . . . . . 94 11.4 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.4.1 dma command register . . . . . . . . . . . . . . . . . 96 11.4.2 dma transfer counter register. . . . . . . . . . . . 97 11.4.3 dcdmaconfiguration register . . . . . . . . . . . . . 98 11.4.4 dma hardware register . . . . . . . . . . . . . . . . . 99 11.4.5 dma interrupt reason register . . . . . . . . . . . . 99 11.4.6 dma interrupt enable register . . . . . . . . . . . 100 11.4.7 dma endpoint register . . . . . . . . . . . . . . . . . 101 11.4.8 dma burst counter register . . . . . . . . . . . . . 102 11.5 general registers . . . . . . . . . . . . . . . . . . . . . 102 11.5.1 dcinterrupt register . . . . . . . . . . . . . . . . . . . . 102 11.5.2 chip id register. . . . . . . . . . . . . . . . . . . . . . . 104 11.5.3 frame number register. . . . . . . . . . . . . . . . . 104 11.5.4 scratch register . . . . . . . . . . . . . . . . . . . . . . 105 11.5.5 unlock device register . . . . . . . . . . . . . . . . . 105 11.5.6 interrupt pulse width register . . . . . . . . . . . . 106 11.5.7 test mode register . . . . . . . . . . . . . . . . . . . . 106 12 limiting values. . . . . . . . . . . . . . . . . . . . . . . . 108 13 recommended operating conditions. . . . . . 108 14 static characteristics. . . . . . . . . . . . . . . . . . . 109 15 dynamic characteristics . . . . . . . . . . . . . . . . 112 15.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 15.1.1 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 15.1.2 pio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 16 package outline . . . . . . . . . . . . . . . . . . . . . . . 125 17 abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 127 18 references . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 128 20 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 21 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 22 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
cd00264885 ? st 2013. all rights reserved. product data sheet rev. 04 ? october 2013 135 of 135 isp1763a hi-speed usb otg controller please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvemen ts, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to an y intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statemen ts and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or regist ered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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